[PATCH] D112408: [RISCV][MC] Add the zve extension according to the v1.0 spec

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:91
   void updateMinVLen();
+  void updateMaxEew();
 };
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There's no definition for this


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:821
 
-let Predicates = [HasStdExtV, IsRV64] in {
-  // Vector Indexed Instructions
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Is this deletion correct? I don't see where the VLUXEI64 instructions are declared now.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:871
+
+def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
+def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>;
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Why is there no Predicate on these aliases?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1509
 
-let Predicates = [HasStdExtZvlsseg, IsRV64] in {
+let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in {
   foreach nf=2-8 in {
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These require RV64 don't they?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D112408/new/

https://reviews.llvm.org/D112408