[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 400282.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112408/new/

https://reviews.llvm.org/D112408

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/add.s
  llvm/test/MC/RISCV/rvv/and.s
  llvm/test/MC/RISCV/rvv/clip.s
  llvm/test/MC/RISCV/rvv/compare.s
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/div.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/fadd.s
  llvm/test/MC/RISCV/rvv/fcompare.s
  llvm/test/MC/RISCV/rvv/fdiv.s
  llvm/test/MC/RISCV/rvv/fmacc.s
  llvm/test/MC/RISCV/rvv/fminmax.s
  llvm/test/MC/RISCV/rvv/fmul.s
  llvm/test/MC/RISCV/rvv/fmv.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/freduction.s
  llvm/test/MC/RISCV/rvv/fsub.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/macc.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/minmax.s
  llvm/test/MC/RISCV/rvv/mul.s
  llvm/test/MC/RISCV/rvv/mv.s
  llvm/test/MC/RISCV/rvv/or.s
  llvm/test/MC/RISCV/rvv/others.s
  llvm/test/MC/RISCV/rvv/reduction.s
  llvm/test/MC/RISCV/rvv/shift.s
  llvm/test/MC/RISCV/rvv/sign-injection.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/sub.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/xor.s

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