[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:155-187
+def FeatureStdExtZvl64b : SubtargetFeature<"experimental-zvl64b", "ZvlLen", "ExtZvl::Zvl64b",
+                       "'Zvl' (Minimum Vector Length) 64",
+                       [FeatureStdExtZvl32b]>;
+def FeatureStdExtZvl128b : SubtargetFeature<"experimental-zvl128b", "ZvlLen", "ExtZvl::Zvl128b",
+                       "'Zvl' (Minimum Vector Length) 128",
+                       [FeatureStdExtZvl64b]>;
+def FeatureStdExtZvl256b : SubtargetFeature<"experimental-zvl256b", "ZvlLen", "ExtZvl::Zvl256b",
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achieveartificialintelligence wrote:
> I think we can write in this way:
> ```
> foreach i = { 5-15 } in {
>   defvar I = !shl(2, i);
>   def FeatureStdExtZvl#I#b
>       : SubtargetFeature<"experimental-zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b",
>                         "'Zvl' (Minimum Vector Length) "#I,
>                         [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
> }
> ```
Thank you for the tip! I previously don't know TableGen can compute values like bit-shift left and do value type casting.

Adapted your code snippet. I modified a bit because `Zvl32b` don't imply anything.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:188
+                       [FeatureStdExtZvl32768b]>;
+def HasStdExtZvl : Predicate<"Subtarget->hasStdExtZvl()">;
+
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craig.topper wrote:
> Is this used?
No it is not, deleted.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694