[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

[Jianjian Guan via Phabricator via cfe-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5475
 
+  if (IndexVT.getVectorElementType() == MVT::i64 && XLenVT == MVT::i32) {
+    report_fatal_error("The V extension does not support EEW=64 for index "
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craig.topper wrote:
> Can we truncate the index to nvxXi32 instead of erroring? Would that allow us to preserve more test cases?
Done, thanks.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:1033
 
-define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i64> %passthru) {
-; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i64:
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craig.topper wrote:
> Can these test cases be preserved in an rv64 only test?
Done, thanks.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518