[clang] d007e66 - [docs] Re-generate ClangCommandLineReference.rst
Fangrui Song via cfe-commits
cfe-commits at lists.llvm.org
Tue Jan 4 16:52:28 PST 2022
Author: Fangrui Song
Date: 2022-01-04T16:52:24-08:00
New Revision: d007e66cb6f58042e043645fda3463de44eb4756
URL: https://github.com/llvm/llvm-project/commit/d007e66cb6f58042e043645fda3463de44eb4756
DIFF: https://github.com/llvm/llvm-project/commit/d007e66cb6f58042e043645fda3463de44eb4756.diff
LOG: [docs] Re-generate ClangCommandLineReference.rst
Added:
Modified:
clang/docs/ClangCommandLineReference.rst
Removed:
################################################################################
diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst
index 97807009fd911..72d571dd10ee3 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -216,6 +216,8 @@ Trivial automatic variable initialization to zero is only here for benchmarks, i
.. option:: -faligned-new=<arg>
+.. option:: -fautomatic
+
.. option:: -ffixed-r19
Reserve register r19 (Hexagon only)
@@ -242,6 +244,10 @@ Specify comma-separated list of triples OpenMP offloading targets to be supporte
.. option:: -force\_load <arg>
.. program:: clang
+.. option:: -fplugin-arg-<name>-<arg>
+
+Pass <arg> to plugin <name>
+
.. option:: -framework <arg>
.. option:: -frtlib-add-rpath, -fno-rtlib-add-rpath
@@ -265,7 +271,7 @@ Build this module as a system module. Only used with -emit-module
Method to generate ID's for compilation units for single source offloading languages CUDA and HIP: 'hash' (ID's generated by hashing file path and command line options) \| 'random' (ID's generated as random numbers) \| 'none' (disabled). Default is 'hash'. This option will be overridden by option '-cuid=\[ID\]' if it is specified.
-.. option:: --gcc-toolchain=<arg>, -gcc-toolchain <arg>
+.. option:: --gcc-toolchain=<arg>
Search for GCC installation in the specified directory on targets which commonly use GCC. The directory usually contains 'lib{,32,64}/gcc{,-cross}/$triple' and 'include'. If specified, sysroot is skipped for GCC detection. Note: executables (e.g. ld) used by the compiler are not overridden by the selected GCC installation
@@ -395,6 +401,10 @@ Do not add include paths for CUDA/HIP and do not include the default CUDA/HIP wr
Do not link device library for CUDA/HIP device compilation
+.. option:: -nohipwrapperinc
+
+Do not include the default HIP wrapper headers and include paths
+
.. option:: -nolibc
.. option:: -nomultidefs
@@ -423,6 +433,10 @@ Disable standard #include directories for the C++ standard library
Write output to <file>
+.. option:: -objcmt-allowlist-dir-path=<arg>, -objcmt-white-list-dir-path=<arg>, -objcmt-whitelist-dir-path=<arg>
+
+Only modify files with a filename contained in the provided directory path
+
.. option:: -objcmt-atomic-property
Make migration to 'atomic' properties
@@ -483,16 +497,20 @@ Enable migration to use NS\_NONATOMIC\_IOSONLY macro for setting property's 'ato
Enable migration to annotate property with NS\_RETURNS\_INNER\_POINTER
-.. option:: -objcmpt-allowlist-dir-path=<arg>, -objcmt-whitelist-dir-path=<arg>, -objcmt-white-list-dir-path=<arg>
+.. option:: -object
-Only modify files with a filename contained in the provided directory path
+.. option:: -object-file-name=<file>, -object-file-name <arg>
-.. option:: -object
+Set the output <file> for debug infos
.. option:: --offload-arch=<arg>, --cuda-gpu-arch=<arg>, --no-offload-arch=<arg>
CUDA offloading device architecture (e.g. sm\_35), or HIP offloading target ID in the form of a device architecture followed by target ID features delimited by a colon. Each target ID feature is a pre-defined string followed by a plus or minus sign (e.g. gfx908:xnack+:sramecc-). May be specified more than once.
+.. option:: --offload=<arg1>,<arg2>...
+
+Specify comma-separated list of offloading target triples (HIP only)
+
.. option:: -p, --profile
.. option:: -pagezero\_size<arg>
@@ -901,13 +919,17 @@ Level of field padding for AddressSanitizer
Enable linker dead stripping of globals in AddressSanitizer
+.. option:: -fsanitize-address-outline-instrumentation, -fno-sanitize-address-outline-instrumentation
+
+Always generate function calls for address sanitizer instrumentation
+
.. option:: -fsanitize-address-poison-custom-array-cookie, -fno-sanitize-address-poison-custom-array-cookie
Enable poisoning array cookies when using custom operator new\[\] in AddressSanitizer
.. option:: -fsanitize-address-use-after-return=<mode>
-Select the mode of detecting stack use-after-return in AddressSanitizer
+Select the mode of detecting stack use-after-return in AddressSanitizer: never \| runtime (default) \| always
.. option:: -fsanitize-address-use-after-scope, -fno-sanitize-address-use-after-scope
@@ -1060,10 +1082,6 @@ Pass the comma separated arguments in <arg> to the preprocessor
Pass <arg> to the preprocessor
-.. option:: -fmacro-prefix-map=<arg>
-
-remap file source paths in predefined preprocessor macros
-
Include path management
-----------------------
@@ -1335,12 +1353,12 @@ Enable the specified warning
Enable warnings for deprecated constructs and define \_\_DEPRECATED
+.. option:: -Wframe-larger-than=<arg>, -Wframe-larger-than
+
.. option:: -Wnonportable-cfstrings<arg>, -Wno-nonportable-cfstrings<arg>
Target-independent compilation options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. option:: -Wframe-larger-than=<arg>
-
.. option:: -fPIC, -fno-PIC
.. option:: -fPIE, -fno-PIE
@@ -1357,6 +1375,10 @@ Emit an address-significance table
.. option:: -falign-functions=<arg>
.. program:: clang
+.. option:: -falign-loops=<N>
+
+N must be a power of two. Align loops to the boundary
+
.. program:: clang1
.. option:: -faligned-allocation, -faligned-new, -fno-aligned-allocation
.. program:: clang
@@ -1371,6 +1393,10 @@ Treat editor placeholders as valid source code
.. option:: -faltivec, -fno-altivec
+.. option:: -faltivec-src-compat=<arg>
+
+Source-level compatibility for Altivec vectors (for PowerPC targets). This includes results of vector comparison (scalar for 'xl', vector for 'gcc') as well as behavior when initializing with a scalar (splatting for 'xl', element zero only for 'gcc'). For 'mixed', the compatibility is as 'gcc' for 'vector bool/vector pixel' and as 'xl' for other types. Current default is 'mixed'.
+
.. option:: -fansi-escape-codes
Use ANSI escape codes for diagnostics
@@ -1391,6 +1417,10 @@ Enable Apple gcc-compatible #pragma pack handling
Restrict code to those available for App Extensions
+.. option:: -fapprox-func, -fno-approx-func
+
+Allow certain math function calls to be replaced with an approximately equivalent calculation
+
.. option:: -fasm, -fno-asm
.. option:: -fasm-blocks, -fno-asm-blocks
@@ -1523,6 +1553,8 @@ Enable C++ exceptions
.. option:: -fcxx-modules, -fno-cxx-modules
+Enable modules for C++
+
.. option:: -fdata-sections, -fno-data-sections
Place each data in its own section
@@ -1677,7 +1709,7 @@ The compilation directory to embed in the debug info and coverage mapping.
.. option:: -ffile-prefix-map=<arg>
-remap file source paths in debug info and predefined preprocessor macros
+remap file source paths in debug info, predefined preprocessor macros and \_\_builtin\_FILE()
.. option:: -ffinite-loops, -fno-finite-loops
@@ -1705,7 +1737,7 @@ Enable support for int128\_t type
.. option:: -ffp-contract=<arg>
-Form fused FP ops (e.g. FMAs): fast (fuses across statements disregarding pragmas) \| on (only fuses in the same statement unless dictated by pragmas) \| off (never fuses) \| fast-honor-pragmas (fuses across statements unless dictated by pragmas). Default is 'fast' for CUDA, 'fast-honor-pragmas' for HIP, and 'on' otherwise.
+Form fused FP ops (e.g. FMAs): fast (fuses across statements disregarding pragmas) \| on (only fuses in the same statement unless dictated by pragmas) \| off (never fuses) \| fast-honor-pragmas (fuses across statements unless diectated by pragmas). Default is 'fast' for CUDA, 'fast-honor-pragmas' for HIP, and 'on' otherwise.
.. option:: -ffp-exception-behavior=<arg>
@@ -1819,29 +1851,19 @@ Enable implicit vector bit-casts
.. option:: -flimited-precision=<arg>
-.. option:: -flto, -fno-lto
-
-Enable LTO in 'full' mode
-
.. option:: -flto-jobs=<arg>
Controls the backend parallelism of -flto=thin (default of 0 means the number of threads will be derived from the number of CPUs detected)
-.. program:: clang1
-.. option:: -flto=<arg>
-.. program:: clang
+.. option:: -flto=<arg>, -flto (equivalent to -flto=full), -flto=auto (equivalent to -flto=full), -flto=jobserver (equivalent to -flto=full)
Set LTO mode to either 'full' or 'thin'
-.. program:: clang2
-.. option:: -flto=auto
-.. program:: clang
+.. option:: -fmacro-backtrace-limit=<arg>
-.. program:: clang3
-.. option:: -flto=jobserver
-.. program:: clang
+.. option:: -fmacro-prefix-map=<arg>
-.. option:: -fmacro-backtrace-limit=<arg>
+remap file source paths in predefined preprocessor macros and \_\_builtin\_FILE()
.. option:: -fmath-errno, -fno-math-errno
@@ -1873,6 +1895,10 @@ Allow merging of constants
Format message diagnostics so that they fit within N columns
+.. option:: -fminimize-whitespace, -fno-minimize-whitespace
+
+Minimize whitespace when emitting preprocessor output
+
.. option:: -fmodule-file-deps, -fno-module-file-deps
.. option:: -fmodule-map-file=<file>
@@ -2017,13 +2043,7 @@ Specify the target Objective-C runtime kind and version
Enable ARC-style weak references in Objective-C
-.. option:: -foffload-lto, -fno-offload-lto
-
-Enable LTO in 'full' mode for offload compilation
-
-.. program:: clang1
-.. option:: -foffload-lto=<arg>
-.. program:: clang
+.. option:: -foffload-lto=<arg>, -foffload-lto (equivalent to -foffload-lto=full)
Set LTO mode to either 'full' or 'thin' for offload compilation
@@ -2033,16 +2053,25 @@ Set LTO mode to either 'full' or 'thin' for offload compilation
Parse OpenMP pragmas and generate parallel code.
+.. option:: -fopenmp-extensions, -fno-openmp-extensions
+
+Enable all Clang extensions for OpenMP directives and clauses
+
.. option:: -fopenmp-simd, -fno-openmp-simd
Emit OpenMP code only for SIMD-based constructs.
-.. option:: -fopenmp-version=<arg>
+.. option:: -fopenmp-target-debug, -fno-openmp-target-debug
-.. option:: -fopenmp-extensions, -fno-openmp-extensions
+Enable debugging in the OpenMP offloading device RTL
+
+.. option:: -fopenmp-target-new-runtime, -fno-openmp-target-new-runtime
+
+Use the new bitcode library for OpenMP offloading
+
+.. option:: -fopenmp-version=<arg>
-Enable or disable all Clang extensions for OpenMP directives and clauses. By
-default, they are enabled.
+Set OpenMP version (e.g. 45 for OpenMP 4.5, 50 for OpenMP 5.0). Default value is 50.
.. program:: clang1
.. option:: -fopenmp=<arg>
@@ -2209,6 +2238,10 @@ Set update method of profile counters (atomic,prefer-atomic,single)
Use instrumentation data for profile-guided optimization. If pathname is a directory, it reads from <pathname>/default.profdata. Otherwise, it reads from file <pathname>.
+.. option:: -fprotect-parens, -fno-protect-parens
+
+Determines whether the optimizer honors parentheses when floating-point expressions are evaluated
+
.. option:: -fpseudo-probe-for-profiling, -fno-pseudo-probe-for-profiling
Emit pseudo probes for sample profiling
@@ -2377,6 +2410,10 @@ Enable optimizations based on the strict rules for overwriting polymorphic C++ o
.. option:: -fstruct-path-tbaa, -fno-struct-path-tbaa
+.. option:: -fswift-async-fp=<option>
+
+Control emission of Swift async extended frame info (option: auto, always, never)
+
.. option:: -fsymbol-partition=<arg>
.. option:: -ftabstop=<arg>
@@ -2484,16 +2521,6 @@ Turn on loop unroller
Use #line in preprocessed output
-.. option:: -fminimize-whitespace, -fno-minimize-whitespace
-
-Ignore the whitespace from the input file when emitting preprocessor
-output. It will only contain whitespace when necessary, e.g. to keep two
-minus signs from merging into to an increment operator. Useful with the
--P option to normalize whitespace such that two files with only formatting
-changes are equal.
-
-Only valid with -E on C-like inputs and incompatible with -traditional-cpp.
-
.. option:: -fvalidate-ast-input-files-content
Compute and store the hash of input files used to build an AST. Files with mismatching mtime's are considered valid if both contents is identical
@@ -2548,14 +2575,12 @@ Give global types 'default' visibility and global functions and variables 'hidde
.. option:: -fvisibility-nodllstorageclass=<arg>
-The visibility for definitions without an explicit DLL export class \[-fvisibility-from-dllstorageclass\]
+The visibility for defintiions without an explicit DLL export class \[-fvisibility-from-dllstorageclass\]
.. option:: -fvisibility=<arg>
Set the default symbol visibility for all global declarations
-.. option:: -fwarn-stack-size=<arg>
-
.. option:: -fwasm-exceptions
Use WebAssembly style exceptions
@@ -2848,6 +2873,12 @@ Reserve the x8 register (AArch64/RISC-V only)
Reserve the x9 register (AArch64/RISC-V only)
+.. option:: -ffuchsia-api-level=<arg>
+
+Set Fuchsia API level
+
+.. option:: -inline-asm=<arg>
+
.. option:: -m16
.. option:: -m32
@@ -2913,7 +2944,7 @@ Specify code object ABI version. Defaults to 3. (AMDGPU only)
.. option:: -mconsole<arg>
.. program:: clang1
-.. option:: -mcpu=<arg>, -mv5 (equivalent to -mcpu=hexagonv5), -mv55 (equivalent to -mcpu=hexagonv55), -mv60 (equivalent to -mcpu=hexagonv60), -mv62 (equivalent to -mcpu=hexagonv62), -mv65 (equivalent to -mcpu=hexagonv65), -mv66 (equivalent to -mcpu=hexagonv66), -mv67 (equivalent to -mcpu=hexagonv67), -mv67t (equivalent to -mcpu=hexagonv67t), -mv68 (equivalent to -mcpu=hexagonv68)
+.. option:: -mcpu=<arg>, -mv5 (equivalent to -mcpu=hexagonv5), -mv55 (equivalent to -mcpu=hexagonv55), -mv60 (equivalent to -mcpu=hexagonv60), -mv62 (equivalent to -mcpu=hexagonv62), -mv65 (equivalent to -mcpu=hexagonv65), -mv66 (equivalent to -mcpu=hexagonv66), -mv67 (equivalent to -mcpu=hexagonv67), -mv67t (equivalent to -mcpu=hexagonv67t), -mv68 (equivalent to -mcpu=hexagonv68), -mv69 (equivalent to -mcpu=hexagonv69)
.. program:: clang
.. option:: -mcrc, -mno-crc
@@ -2948,6 +2979,10 @@ Insert calls to fentry at function entry (x86/SystemZ only)
.. option:: -mfpu=<arg>
+.. option:: -mgeneral-regs-only
+
+Generate code which only uses the general purpose registers (AArch64/x86 only)
+
.. option:: -mglobal-merge, -mno-global-merge
Enable merging of globals
@@ -3064,6 +3099,10 @@ Select return address signing scope
.. option:: -msim
+.. option:: -mskip-rax-setup, -mno-skip-rax-setup
+
+Skip setting up RAX register when passing variable arguments (x86 only)
+
.. option:: -msoft-float, -mno-soft-float
Use software floating point
@@ -3102,6 +3141,10 @@ Force realign the stack at entry to every function
Return small structs in registers (PPC32 only)
+.. option:: -mtargetos=<arg>
+
+Set the deployment target to be the specified OS and OS version
+
.. option:: -mthread-model <arg>
The thread model to use, e.g. posix, single (posix by default)
@@ -3188,10 +3231,6 @@ Make the x9 register call-saved (AArch64 only)
Workaround Cortex-A53 erratum 835769 (AArch64 only)
-.. option:: -mgeneral-regs-only
-
-Generate code which only uses the general purpose registers (AArch64 only)
-
.. option:: -mmark-bti-property
Add .note.gnu.property with BTI to assembly files (AArch64 only)
@@ -3200,6 +3239,14 @@ Add .note.gnu.property with BTI to assembly files (AArch64 only)
Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only)
+.. option:: -mvscale-max=<arg>
+
+Specify the vscale maximum. Defaults to the vector length agnostic value of "0". (AArch64 only)
+
+.. option:: -mvscale-min=<arg>
+
+Specify the vscale minimum. Defaults to "1". (AArch64 only)
+
AMDGPU
------
.. option:: -mcumode, -mno-cumode
@@ -3228,13 +3275,17 @@ Reserve the r9 register (ARM only)
Allow use of CMSE (Armv8-M Security Extensions)
+.. option:: -mexecute-only, -mno-execute-only, -mpure-code
+
+Disallow generation of data access to code sections (ARM only)
+
.. option:: -mfix-cmse-cve-2021-35465, -mno-fix-cmse-cve-2021-35465
-Enable the cve-2021-35465 security vulnerability mitigation (ARM only).
+Work around VLLDM erratum CVE-2021-35465 (ARM only)
-.. option:: -mexecute-only, -mno-execute-only, -mpure-code
+.. option:: -mno-bti-at-return-twice
-Disallow generation of data access to code sections (ARM only)
+Do not add a BTI instruction after a setjmp or other return-twice construct (Arm only)
.. option:: -mno-movt
@@ -3260,13 +3311,12 @@ Thread pointer access method (AArch32/AArch64 only)
Allow memory accesses to be unaligned (AArch32/AArch64 only)
-.. option:: -mno-bti-at-return-twice
-
-Do not add a BTI instruction after a setjmp or other return-twice construct (Arm
-only)
-
Hexagon
-------
+.. option:: -mhvx-ieee-fp, -mno-hvx-ieee-fp
+
+Enable Hexagon HVX IEEE floating-point
+
.. option:: -mieee-rnd-near
.. option:: -mmemops, -mno-memops
@@ -3295,6 +3345,10 @@ Enable Hexagon Vector eXtensions
Set Hexagon Vector Length
+.. option:: -mhvx-qfloat, -mno-hvx-qfloat
+
+Enable Hexagon HVX QFloat instructions
+
.. program:: clang1
.. option:: -mhvx=<arg>
.. program:: clang
@@ -3401,6 +3455,8 @@ Place constants in the .rodata section instead of the .sdata section even if the
Assume that externally defined data is in the small data if it meets the -G <size> threshold (MIPS)
+.. option:: -mfix4300
+
.. option:: -mfp32
Use 32-bit floating point registers (MIPS only)
@@ -3521,6 +3577,8 @@ WebAssembly
.. option:: -mreference-types, -mno-reference-types
+.. option:: -mrelaxed-simd, -mno-relaxed-simd
+
.. option:: -msign-ext, -mno-sign-ext
.. option:: -msimd128, -mno-simd128
@@ -3848,6 +3906,8 @@ Embed source text in DWARF debug sections
.. option:: -grecord-command-line, -gno-record-command-line, -grecord-gcc-switches
+.. option:: -gsimple-template-names, -gno-simple-template-names
+
.. option:: -gsplit-dwarf, -gno-split-dwarf
.. program:: clang1
@@ -3887,8 +3947,6 @@ a Fortran input.
.. option:: -fall-intrinsics, -fno-all-intrinsics
-.. option:: -fautomatic, -fno-automatic
-
.. option:: -fbacktrace, -fno-backtrace
.. option:: -fblas-matmul-limit=<arg>
@@ -3953,8 +4011,6 @@ a Fortran input.
.. option:: -fpack-derived, -fno-pack-derived
-.. option:: -fprotect-parens, -fno-protect-parens
-
.. option:: -frange-check, -fno-range-check
.. option:: -freal-4-real-10, -fno-real-4-real-10
@@ -4031,6 +4087,10 @@ Pass <arg> to the linker
.. option:: -Z
.. program:: clang
+.. option:: -b<arg>
+
+Pass -b <arg> to the linker on AIX (only).
+
.. option:: -coverage, --coverage
.. option:: -e<arg>, --entry
@@ -4041,6 +4101,10 @@ Pass <arg> to the linker
HIP device library
+.. option:: --hipspv-pass-plugin=<dsopath>
+
+path to a pass plugin for HIP to SPIR-V passes.
+
.. option:: -l<arg>
.. option:: --ld-path=<arg>
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