[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added inline comments.


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Comment at: llvm/lib/Support/RISCVISAInfo.cpp:741-751
+    {{"zvl1024b"}, {ImpliedExtsZvl1024b}},
+    {{"zvl128b"}, {ImpliedExtsZvl128b}},
+    {{"zvl16384b"}, {ImpliedExtsZvl16384b}},
+    {{"zvl2048b"}, {ImpliedExtsZvl2048b}},
+    {{"zvl256b"}, {ImpliedExtsZvl256b}},
+    {{"zvl32768b"}, {ImpliedExtsZvl32768b}},
+    {{"zvl4096b"}, {ImpliedExtsZvl4096b}},
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Can we compress the code?


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Comment at: llvm/lib/Target/RISCV/RISCV.td:153-186
+def FeatureStdExtZvl32b : SubtargetFeature<"experimental-zvl32b", "ZvlLen", "ExtZvl::Zvl32b",
+                       "'Zvl' (Minimum Vector Length) 32">;
+def FeatureStdExtZvl64b : SubtargetFeature<"experimental-zvl64b", "ZvlLen", "ExtZvl::Zvl64b",
+                       "'Zvl' (Minimum Vector Length) 64",
+                       [FeatureStdExtZvl32b]>;
+def FeatureStdExtZvl128b : SubtargetFeature<"experimental-zvl128b", "ZvlLen", "ExtZvl::Zvl128b",
+                       "'Zvl' (Minimum Vector Length) 128",
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Same as here.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694