[PATCH] D116161: [Clang] Add an overload for emitUnaryBuiltin.
Jun Zhang via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Fri Dec 24 06:23:56 PST 2021
junaire added a comment.
I confirmed that we can use `emitUnaryBuiltin` in the cases you pointed out. Please see the logs below:
$ path/to/llvm-project/build/bin/clang -cc1 -internal-isystem /path/to/llvm-project/build/lib/clang/14.0.0/include -nostdsysteminc -triple x86_64-apple-darwin /path/to/llvm-project/clang/test/CodeGen/builtins-elementwise-math.c -emit-llvm -disable-llvm-passes -o - | /path/to/llvm-project/build/bin/FileCheck /path/to/llvm-project/clang/test/CodeGen/builtins-elementwise-math.c
/path/to/llvm-project/clang/test/CodeGen/builtins-elementwise-math.c:16:17: error: CHECK-NEXT: expected string not found in input
// CHECK-NEXT: call float @llvm.fabs.f32(float [[F1]])
^
<stdin>:35:43: note: scanning from here
%0 = load float, float* %f1.addr, align 4
^
<stdin>:35:43: note: with "F1" equal to "%0"
%0 = load float, float* %f1.addr, align 4
^
<stdin>:37:13: note: possible intended match here
%elt.abs = call float @llvm.fabs.f32(float %1)
^
Input file: <stdin>
Check file: /path/to/llvm-project/clang/test/CodeGen/builtins-elementwise-math.c
-dump-input=help explains the following input dump.
Input was:
<<<<<<
30: store <8 x i16> %vi1, <8 x i16>* %vi1.addr, align 16
31: store <8 x i16> %vi2, <8 x i16>* %vi2.addr, align 16
32: store i64 %i1, i64* %i1.addr, align 8
33: store i64 %i2, i64* %i2.addr, align 8
34: store i16 %si, i16* %si.addr, align 2
35: %0 = load float, float* %f1.addr, align 4
next:16'0 X error: no match found
next:16'1 with "F1" equal to "%0"
36: %1 = load float, float* %f1.addr, align 4
next:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
37: %elt.abs = call float @llvm.fabs.f32(float %1)
next:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:16'2 ? possible intended match
38: store float %elt.abs, float* %f2.addr, align 4
next:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
39: %2 = load double, double* %d1.addr, align 8
next:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
40: %3 = load double, double* %d1.addr, align 8
next:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
41: %elt.abs1 = call double @llvm.fabs.f64(double %3)
next:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
42: store double %elt.abs1, double* %d2.addr, align 8
next:16'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>>>
$ /path/to/llvm-project/build/bin/clang -cc1 -internal-isystem /path/to/llvm-project/build/lib/clang/14.0.0/include -nostdsysteminc -triple x86_64-apple-darwin ~/dev/cpp-projects/llvm-project/clang/test/CodeGen/builtins-reduction-math.c -emit-llvm -disable-llvm-passes -o - | ~/dev/cpp-projects/llvm-project/build/bin/FileCheck ~/dev/cpp-projects/llvm-project/clang/test/CodeGen/builtins-reduction-math.c
/path/to/llvm-project/clang/test/CodeGen/builtins-reduction-math.c:12:17: error: CHECK-NEXT: expected string not found in input
// CHECK-NEXT: call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[VF1]])
^
<stdin>:23:57: note: scanning from here
%0 = load <4 x float>, <4 x float>* %vf1.addr, align 16
^
<stdin>:23:57: note: with "VF1" equal to "%0"
%0 = load <4 x float>, <4 x float>* %vf1.addr, align 16
^
<stdin>:25:13: note: possible intended match here
%rdx.min = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %1)
^
/path/to/llvm-project/clang/test/CodeGen/builtins-reduction-math.c:38:17: error: CHECK-NEXT: expected string not found in input
// CHECK-NEXT: call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[VF1]])
^
<stdin>:74:57: note: scanning from here
%0 = load <4 x float>, <4 x float>* %vf1.addr, align 16
^
<stdin>:74:57: note: with "VF1" equal to "%0"
%0 = load <4 x float>, <4 x float>* %vf1.addr, align 16
^
<stdin>:76:13: note: possible intended match here
%rdx.min = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %1)
^
Input file: <stdin>
Check file: /path/to/llvm-project/clang/test/CodeGen/builtins-reduction-math.c
-dump-input=help explains the following input dump.
Input was:
<<<<<<
18: %cvi1 = alloca <8 x i16>, align 16
19: %r5 = alloca i64, align 8
20: store <4 x float> %vf1, <4 x float>* %vf1.addr, align 16
21: store <8 x i16> %vi1, <8 x i16>* %vi1.addr, align 16
22: store <4 x i32> %vu1, <4 x i32>* %vu1.addr, align 16
23: %0 = load <4 x float>, <4 x float>* %vf1.addr, align 16
next:12'0 X error: no match found
next:12'1 with "VF1" equal to "%0"
24: %1 = load <4 x float>, <4 x float>* %vf1.addr, align 16
next:12'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
25: %rdx.min = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %1)
next:12'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:12'2 ? possible intended match
26: store float %rdx.min, float* %r1, align 4
next:12'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27: %2 = load <8 x i16>, <8 x i16>* %vi1.addr, align 16
next:12'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
28: %3 = load <8 x i16>, <8 x i16>* %vi1.addr, align 16
next:12'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29: %rdx.min1 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %3)
next:12'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
30: store i16 %rdx.min1, i16* %r2, align 2
next:12'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
69: %cvi1 = alloca <8 x i16>, align 16
70: %r5 = alloca i64, align 8
71: store <4 x float> %vf1, <4 x float>* %vf1.addr, align 16
72: store <8 x i16> %vi1, <8 x i16>* %vi1.addr, align 16
73: store <4 x i32> %vu1, <4 x i32>* %vu1.addr, align 16
74: %0 = load <4 x float>, <4 x float>* %vf1.addr, align 16
next:38'0 X error: no match found
next:38'1 with "VF1" equal to "%0"
75: %1 = load <4 x float>, <4 x float>* %vf1.addr, align 16
next:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
76: %rdx.min = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %1)
next:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:38'2 ? possible intended match
77: store float %rdx.min, float* %r1, align 4
next:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
78: %2 = load <8 x i16>, <8 x i16>* %vi1.addr, align 16
next:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
79: %3 = load <8 x i16>, <8 x i16>* %vi1.addr, align 16
next:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
80: %rdx.min1 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %3)
next:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
81: store i16 %rdx.min1, i16* %r2, align 2
next:38'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>>>
Do you know why these will happen? @fhahn
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D116161/new/
https://reviews.llvm.org/D116161
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