[clang] 1201a0f - [OpenMP] Fix incorrect type when casting from uintptr
Nikita Popov via cfe-commits
cfe-commits at lists.llvm.org
Wed Dec 22 23:59:37 PST 2021
Author: Nikita Popov
Date: 2021-12-23T08:57:11+01:00
New Revision: 1201a0f3955b7b564db3e5a913a7ec9255f9275d
URL: https://github.com/llvm/llvm-project/commit/1201a0f3955b7b564db3e5a913a7ec9255f9275d
DIFF: https://github.com/llvm/llvm-project/commit/1201a0f3955b7b564db3e5a913a7ec9255f9275d.diff
LOG: [OpenMP] Fix incorrect type when casting from uintptr
MakeNaturalAlignAddrLValue() expects the pointee type, but the
pointer type was passed. As a result, the natural alignment of
the pointer (usually 8) was always used in place of the natural
alignment of the value type.
Differential Revision: https://reviews.llvm.org/D116171
Added:
Modified:
clang/lib/CodeGen/CGStmtOpenMP.cpp
clang/test/OpenMP/debug-info-complex-byval.cpp
clang/test/OpenMP/distribute_parallel_for_codegen.cpp
clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
clang/test/OpenMP/nvptx_parallel_codegen.cpp
clang/test/OpenMP/nvptx_parallel_for_codegen.cpp
clang/test/OpenMP/nvptx_target_codegen.cpp
clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp
clang/test/OpenMP/nvptx_target_printf_codegen.c
clang/test/OpenMP/nvptx_target_teams_codegen.cpp
clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
clang/test/OpenMP/nvptx_teams_codegen.cpp
clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
clang/test/OpenMP/parallel_firstprivate_codegen.cpp
clang/test/OpenMP/parallel_for_codegen.cpp
clang/test/OpenMP/parallel_master_codegen.cpp
clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
clang/test/OpenMP/single_codegen.cpp
clang/test/OpenMP/target_codegen_global_capture.cpp
clang/test/OpenMP/target_parallel_codegen.cpp
clang/test/OpenMP/target_parallel_debug_codegen.cpp
clang/test/OpenMP/target_parallel_for_codegen.cpp
clang/test/OpenMP/target_parallel_for_debug_codegen.cpp
clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
clang/test/OpenMP/target_parallel_if_codegen.cpp
clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
clang/test/OpenMP/target_teams_codegen.cpp
clang/test/OpenMP/target_teams_distribute_codegen.cpp
clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp
clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp
clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp
clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp
clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp
clang/test/OpenMP/target_teams_num_teams_codegen.cpp
clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
clang/test/OpenMP/teams_codegen.cpp
clang/test/OpenMP/teams_distribute_codegen.cpp
clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp
clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
clang/test/OpenMP/teams_distribute_simd_codegen.cpp
clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp
clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp
clang/test/OpenMP/teams_firstprivate_codegen.cpp
clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected
Removed:
################################################################################
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index 5677fce355d55..1bc086ffb1c6f 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -378,8 +378,7 @@ static Address castValueFromUintptr(CodeGenFunction &CGF, SourceLocation Loc,
AddrLV.getAddress(CGF).getPointer(), Ctx.getUIntPtrType(),
Ctx.getPointerType(DstType), Loc);
Address TmpAddr =
- CGF.MakeNaturalAlignAddrLValue(CastedPtr, Ctx.getPointerType(DstType))
- .getAddress(CGF);
+ CGF.MakeNaturalAlignAddrLValue(CastedPtr, DstType).getAddress(CGF);
return TmpAddr;
}
diff --git a/clang/test/OpenMP/debug-info-complex-byval.cpp b/clang/test/OpenMP/debug-info-complex-byval.cpp
index cc39d65bc414d..c66cc0b384da5 100644
--- a/clang/test/OpenMP/debug-info-complex-byval.cpp
+++ b/clang/test/OpenMP/debug-info-complex-byval.cpp
@@ -57,7 +57,7 @@ void a() {
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG38]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG38]]
// CHECK1-NEXT: [[TMP2:%.*]] = bitcast { float, float }* [[CONV]] to <2 x float>*, !dbg [[DBG38]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 8, !dbg [[DBG38]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 4, !dbg [[DBG38]]
// CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP0]], i32* [[TMP1]], <2 x float> [[TMP3]]) #[[ATTR4:[0-9]+]], !dbg [[DBG38]]
// CHECK1-NEXT: ret void, !dbg [[DBG38]]
//
diff --git a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp
index d1a3f33c33d9c..1ed8db15f9793 100644
--- a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp
@@ -1969,7 +1969,7 @@ int main() {
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -2482,7 +2482,7 @@ int main() {
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -3761,7 +3761,7 @@ int main() {
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -4274,7 +4274,7 @@ int main() {
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -9456,7 +9456,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -9949,7 +9949,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -11673,7 +11673,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -12166,7 +12166,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -13885,7 +13885,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -14378,7 +14378,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -16102,7 +16102,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -16595,7 +16595,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
diff --git a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
index 9982bb790447b..4eda6d07645bd 100644
--- a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
@@ -489,8 +489,8 @@ int main() {
// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8
// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8
-// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 8
-// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8
+// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 4
+// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -749,8 +749,8 @@ int main() {
// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8
// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8
-// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 8
-// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8
+// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 4
+// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -1702,7 +1702,7 @@ int main() {
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
@@ -2150,7 +2150,7 @@ int main() {
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -2640,7 +2640,7 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
@@ -3088,7 +3088,7 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
diff --git a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
index dec264ff9ea1c..21c59d5ae125b 100644
--- a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
@@ -62,7 +62,7 @@ int main(int argc, char **argv) {
// CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK1-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
@@ -681,7 +681,7 @@ int main(int argc, char **argv) {
// CHECK2-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
// CHECK2-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
index 60b4685ed9b46..9c21a8789bc0a 100644
--- a/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
@@ -2077,7 +2077,7 @@ int main() {
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -2638,7 +2638,7 @@ int main() {
// CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -4037,7 +4037,7 @@ int main() {
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -4598,7 +4598,7 @@ int main() {
// CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -10344,7 +10344,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -10885,7 +10885,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -12714,7 +12714,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -13255,7 +13255,7 @@ int main() {
// CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -15094,7 +15094,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -15635,7 +15635,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -17464,7 +17464,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP10]])
@@ -18005,7 +18005,7 @@ int main() {
// CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
index 56640954d5140..887117773d6e2 100644
--- a/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
@@ -495,8 +495,8 @@ int main() {
// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8
// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8
// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
-// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8
-// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8
+// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 4, !llvm.access.group !8
+// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4, !llvm.access.group !8
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -769,8 +769,8 @@ int main() {
// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8
// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8
// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8
-// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8
-// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8
+// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 4, !llvm.access.group !8
+// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 4, !llvm.access.group !8
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -1818,7 +1818,7 @@ int main() {
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
-// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
@@ -2280,7 +2280,7 @@ int main() {
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -2784,7 +2784,7 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
-// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
@@ -3246,7 +3246,7 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
index 52d2c6cc7768a..a5c1ca79380ac 100644
--- a/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
@@ -3817,7 +3817,7 @@ int main() {
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -3945,7 +3945,7 @@ int main() {
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -5465,7 +5465,7 @@ int main() {
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -5593,7 +5593,7 @@ int main() {
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -11083,7 +11083,7 @@ int main() {
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -11211,7 +11211,7 @@ int main() {
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -12731,7 +12731,7 @@ int main() {
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -12859,7 +12859,7 @@ int main() {
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
diff --git a/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp b/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
index 287119f3f6a91..c8e95951a61f9 100644
--- a/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
@@ -2999,7 +2999,7 @@ int main(int argc, char **argv) {
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK4: user_code.entry:
// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
-// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP6]], i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
@@ -3048,7 +3048,7 @@ int main(int argc, char **argv) {
// CHECK4-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[D_ADDR]], align 8
// CHECK4-NEXT: [[C1:%.*]] = call i8* @__kmpc_alloc_shared(i64 40)
// CHECK4-NEXT: [[C_ON_STACK:%.*]] = bitcast i8* [[C1]] to [10 x i32]*
-// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
diff --git a/clang/test/OpenMP/nvptx_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_parallel_codegen.cpp
index 15379282e853c..5c33af3872960 100644
--- a/clang/test/OpenMP/nvptx_parallel_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_parallel_codegen.cpp
@@ -1457,9 +1457,9 @@ int bar(int n){
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 0, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP3]], i64 0)
// CHECK1-NEXT: [[TMP4:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS2]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__2 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__2_wrapper to i8*), i8** [[TMP4]], i64 0)
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
@@ -1568,19 +1568,19 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1000
// CHECK1-NEXT: [[TMP4:%.*]] = zext i1 [[CMP]] to i32
// CHECK1-NEXT: [[TMP5:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 [[TMP4]], i32 -1, i32 -1, i8* bitcast (void (i32*, i32*)* @__omp_outlined__3 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*), i8** [[TMP5]], i64 0)
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV1]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP7]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV2]], align 8
+// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV2]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], 1
@@ -1632,7 +1632,7 @@ int bar(int n){
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[A1:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[A_ON_STACK:%.*]] = bitcast i8* [[A1]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[A_ON_STACK]], align 4
@@ -1849,11 +1849,11 @@ int bar(int n){
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP7]] to i32
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
diff --git a/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp
index fdd3cd6db8cf3..b0738928a013c 100644
--- a/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp
@@ -472,7 +472,7 @@ int bar(int n){
// CHECK-NEXT: [[D:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D]] to i32*
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK-NEXT: store i32 [[TMP3]], i32* [[D_ON_STACK]], align 4
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-NEXT: [[TMP5:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
diff --git a/clang/test/OpenMP/nvptx_target_codegen.cpp b/clang/test/OpenMP/nvptx_target_codegen.cpp
index 34fc9d94501fc..c3a90d523110c 100644
--- a/clang/test/OpenMP/nvptx_target_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_codegen.cpp
@@ -215,16 +215,16 @@ void unreachable_call() {
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
@@ -265,9 +265,9 @@ void unreachable_call() {
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP10]] to double
@@ -342,19 +342,19 @@ void unreachable_call() {
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i32
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP5]], 1
@@ -387,7 +387,7 @@ void unreachable_call() {
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP5]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -468,14 +468,14 @@ void unreachable_call() {
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 1
@@ -602,16 +602,16 @@ void unreachable_call() {
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
@@ -730,16 +730,16 @@ void unreachable_call() {
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK2-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK2-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1
@@ -854,11 +854,11 @@ void unreachable_call() {
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK2-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1
@@ -985,16 +985,16 @@ void unreachable_call() {
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry:
-// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 2
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
// CHECK3-NEXT: ret void
// CHECK3: worker.exit:
@@ -1113,16 +1113,16 @@ void unreachable_call() {
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP5]], 1
@@ -1237,11 +1237,11 @@ void unreachable_call() {
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP4]], 1
diff --git a/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp
index 5049500516f6b..6e9385456492c 100644
--- a/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp
@@ -108,7 +108,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8*
// CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
@@ -439,7 +439,7 @@ int bar(int n){
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK4: user_code.entry:
// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
-// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK4-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8*
// CHECK4-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8
diff --git a/clang/test/OpenMP/nvptx_target_printf_codegen.c b/clang/test/OpenMP/nvptx_target_printf_codegen.c
index 99b48cc792b27..b3e258d30d77b 100644
--- a/clang/test/OpenMP/nvptx_target_printf_codegen.c
+++ b/clang/test/OpenMP/nvptx_target_printf_codegen.c
@@ -93,7 +93,7 @@ void CheckAllocaIsInEntryBlock() {
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
// CHECK-64: if.then:
diff --git a/clang/test/OpenMP/nvptx_target_teams_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_codegen.cpp
index fbe62f191eec6..53ca71dbcd9bd 100644
--- a/clang/test/OpenMP/nvptx_target_teams_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_teams_codegen.cpp
@@ -63,7 +63,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -86,7 +86,7 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK1-NEXT: store i8 49, i8* [[CONV]], align 8
+// CHECK1-NEXT: store i8 49, i8* [[CONV]], align 1
// CHECK1-NEXT: ret void
//
//
@@ -104,7 +104,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -127,7 +127,7 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: store i16 1, i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 1, i16* [[CONV]], align 2
// CHECK1-NEXT: ret void
//
//
@@ -145,7 +145,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -228,7 +228,7 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
@@ -251,7 +251,7 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8*
-// CHECK2-NEXT: store i8 49, i8* [[CONV]], align 4
+// CHECK2-NEXT: store i8 49, i8* [[CONV]], align 1
// CHECK2-NEXT: ret void
//
//
@@ -269,7 +269,7 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -292,7 +292,7 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: store i16 1, i16* [[CONV]], align 4
+// CHECK2-NEXT: store i16 1, i16* [[CONV]], align 2
// CHECK2-NEXT: ret void
//
//
@@ -310,7 +310,7 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -393,7 +393,7 @@ int bar(int n){
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
@@ -416,7 +416,7 @@ int bar(int n){
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[A_ADDR]] to i8*
-// CHECK3-NEXT: store i8 49, i8* [[CONV]], align 4
+// CHECK3-NEXT: store i8 49, i8* [[CONV]], align 1
// CHECK3-NEXT: ret void
//
//
@@ -434,7 +434,7 @@ int bar(int n){
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -457,7 +457,7 @@ int bar(int n){
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: store i16 1, i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 1, i16* [[CONV]], align 2
// CHECK3-NEXT: ret void
//
//
@@ -475,7 +475,7 @@ int bar(int n){
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry:
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
index d0b57801530b6..0cd88fb9b12ce 100644
--- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
@@ -18488,11 +18488,11 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8
@@ -18536,7 +18536,7 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -18583,11 +18583,11 @@ int bar(int n){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8
@@ -18650,8 +18650,8 @@ int bar(int n){
// CHECK1-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
// CHECK1-NEXT: br i1 [[TMP49]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then:
-// CHECK1-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 8
-// CHECK1-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 4
+// CHECK1-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
@@ -18690,7 +18690,7 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -18756,7 +18756,7 @@ int bar(int n){
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4
-// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18785,8 +18785,8 @@ int bar(int n){
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK1-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then:
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 8
-// CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 4
+// CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
@@ -18811,7 +18811,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -18849,7 +18849,7 @@ int bar(int n){
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -18897,7 +18897,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -18985,7 +18985,7 @@ int bar(int n){
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -19257,7 +19257,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8
@@ -19326,7 +19326,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8
@@ -19445,7 +19445,7 @@ int bar(int n){
// CHECK1-NEXT: store i32 10, i32* [[K]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]]
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4
@@ -19490,7 +19490,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -19532,9 +19532,9 @@ int bar(int n){
// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -19592,7 +19592,7 @@ int bar(int n){
// CHECK1: omp.inner.for.body:
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
// CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV15]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -19684,9 +19684,9 @@ int bar(int n){
// CHECK1-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -19809,7 +19809,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -19850,7 +19850,7 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -19898,7 +19898,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -19992,7 +19992,7 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -20082,11 +20082,11 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8
@@ -20130,7 +20130,7 @@ int bar(int n){
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK2-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK2-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -20177,11 +20177,11 @@ int bar(int n){
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8
@@ -20244,8 +20244,8 @@ int bar(int n){
// CHECK2-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
// CHECK2-NEXT: br i1 [[TMP49]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then:
-// CHECK2-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 8
-// CHECK2-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP50:%.*]] = load i32, i32* [[CONV1]], align 4
+// CHECK2-NEXT: store i32 [[TMP50]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
@@ -20284,7 +20284,7 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -20350,7 +20350,7 @@ int bar(int n){
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK2-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4
-// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -20379,8 +20379,8 @@ int bar(int n){
// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
// CHECK2-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK2: .omp.lastprivate.then:
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 8
-// CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[CONV1]], align 4
+// CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
@@ -20405,7 +20405,7 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20443,7 +20443,7 @@ int bar(int n){
// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -20491,7 +20491,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20579,7 +20579,7 @@ int bar(int n){
// CHECK2-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -20851,7 +20851,7 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8
@@ -20920,7 +20920,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8
@@ -21039,7 +21039,7 @@ int bar(int n){
// CHECK2-NEXT: store i32 10, i32* [[K]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]]
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4
@@ -21084,7 +21084,7 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -21126,9 +21126,9 @@ int bar(int n){
// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -21185,7 +21185,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV12]], align 4
// CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -21277,9 +21277,9 @@ int bar(int n){
// CHECK2-NEXT: store [10 x [10 x i32]]* [[C]], [10 x [10 x i32]]** [[C_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -21398,7 +21398,7 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -21439,7 +21439,7 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -21487,7 +21487,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -21581,7 +21581,7 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[V]], i32** [[V_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
index 98cfc7aa0db51..fd65a077c5d8f 100644
--- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
@@ -50,11 +50,11 @@ int main(int argc, char **argv) {
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -96,7 +96,7 @@ int main(int argc, char **argv) {
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -144,11 +144,11 @@ int main(int argc, char **argv) {
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -242,7 +242,7 @@ int main(int argc, char **argv) {
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -265,7 +265,7 @@ int main(int argc, char **argv) {
// CHECK1-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -948,11 +948,11 @@ int main(int argc, char **argv) {
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK4: user_code.entry:
// CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
-// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
-// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -994,7 +994,7 @@ int main(int argc, char **argv) {
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1042,11 +1042,11 @@ int main(int argc, char **argv) {
// CHECK4-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
-// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -1140,7 +1140,7 @@ int main(int argc, char **argv) {
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1163,7 +1163,7 @@ int main(int argc, char **argv) {
// CHECK4-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
index 754f4ce08ca09..0339a6d21899e 100644
--- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
@@ -9401,11 +9401,11 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[L_CASTED]], align 8
@@ -9449,7 +9449,7 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
// CHECK1-NEXT: [[L2:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[L_ON_STACK:%.*]] = bitcast i8* [[L2]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -9496,11 +9496,11 @@ int bar(int n){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !12
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[L_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[L_CASTED]], align 8, !llvm.access.group !12
@@ -9575,8 +9575,8 @@ int bar(int n){
// CHECK1-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
// CHECK1-NEXT: br i1 [[TMP52]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then:
-// CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[CONV1]], align 8
-// CHECK1-NEXT: store i32 [[TMP53]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[CONV1]], align 4
+// CHECK1-NEXT: store i32 [[TMP53]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
@@ -9615,7 +9615,7 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[L_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -9681,7 +9681,7 @@ int bar(int n){
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
// CHECK1-NEXT: store i32 1, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !16
-// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8, !llvm.access.group !16
+// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4, !llvm.access.group !16
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9722,8 +9722,8 @@ int bar(int n){
// CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
// CHECK1-NEXT: br i1 [[TMP32]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK1: .omp.lastprivate.then:
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[CONV1]], align 8
-// CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[CONV1]], align 4
+// CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
@@ -9748,7 +9748,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -9786,7 +9786,7 @@ int bar(int n){
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -9834,7 +9834,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !19
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !19
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !19
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !19
@@ -9934,7 +9934,7 @@ int bar(int n){
// CHECK1-NEXT: store [1000 x i16]* [[AA]], [1000 x i16]** [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i16]*, [1000 x i16]** [[AA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -10232,7 +10232,7 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[F_CASTED]], align 8
@@ -10301,7 +10301,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !31
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[F_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4, !llvm.access.group !31
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[F_CASTED]], align 8, !llvm.access.group !31
@@ -10428,7 +10428,7 @@ int bar(int n){
// CHECK1-NEXT: store i32 10, i32* [[K]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !34
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP11]], [[MUL9]]
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[K]], align 4, !llvm.access.group !34
diff --git a/clang/test/OpenMP/nvptx_teams_codegen.cpp b/clang/test/OpenMP/nvptx_teams_codegen.cpp
index cc7050a7cb07e..52d94ab9b682d 100644
--- a/clang/test/OpenMP/nvptx_teams_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_teams_codegen.cpp
@@ -902,7 +902,7 @@ int main (int argc, char **argv) {
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARGC1:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[ARGC_ON_STACK:%.*]] = bitcast i8* [[ARGC1]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
@@ -1069,7 +1069,7 @@ int main (int argc, char **argv) {
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry:
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK3-NEXT: [[ARGC3:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK3-NEXT: [[ARGC_ON_STACK:%.*]] = bitcast i8* [[ARGC3]] to i32*
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[ARGC_ON_STACK]], align 4
diff --git a/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp b/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
index d0a19bdb43964..f584b2b4676ce 100644
--- a/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
@@ -4520,10 +4520,10 @@ int bar(int n){
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
-// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i64 1)
// CHECK1-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1
-// CHECK1-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4
// CHECK1-NEXT: [[D3:%.*]] = call i8* @__kmpc_alloc_shared(i64 4)
// CHECK1-NEXT: [[D_ON_STACK:%.*]] = bitcast i8* [[D3]] to float*
// CHECK1-NEXT: store float [[TMP2]], float* [[D_ON_STACK]], align 4
@@ -5839,7 +5839,7 @@ int bar(int n){
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
-// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i32 1)
// CHECK2-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1
// CHECK2-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4
@@ -7157,7 +7157,7 @@ int bar(int n){
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK3: user_code.entry:
-// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[C2:%.*]] = call i8* @__kmpc_alloc_shared(i32 1)
// CHECK3-NEXT: store i8 [[TMP1]], i8* [[C2]], align 1
// CHECK3-NEXT: [[TMP2:%.*]] = load float, float* [[CONV1]], align 4
diff --git a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp
index 7542169b574b5..a777faf5f03d0 100644
--- a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp
@@ -2300,14 +2300,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
-// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
@@ -2379,7 +2379,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK9-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*))
// CHECK9-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8*
@@ -2521,9 +2521,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK9-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
-// CHECK9-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1
@@ -2999,14 +2999,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
-// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
@@ -3078,7 +3078,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK10-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*))
// CHECK10-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8*
@@ -3220,9 +3220,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
// CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK10-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4
-// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
-// CHECK10-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1
@@ -3763,9 +3763,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
-// CHECK11-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK11-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
@@ -3791,7 +3791,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK11-NEXT: store i32 1, i32* [[G1]], align 128
-// CHECK11-NEXT: store i32 2, i32* [[CONV]], align 8
+// CHECK11-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0
// CHECK11-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1
@@ -3879,7 +3879,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK12-NEXT: store i32 1, i32* [[G1]], align 128
-// CHECK12-NEXT: store i32 2, i32* [[CONV]], align 8
+// CHECK12-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 0
// CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128
// CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 1
@@ -3894,7 +3894,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK12-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128
// CHECK12-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128
// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5
-// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 32
// CHECK12-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]] to void ()*
// CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic*
@@ -4029,7 +4029,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8
-// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED7]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7
// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP3]], align 8
@@ -4119,9 +4119,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
// CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
-// CHECK12-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK12-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
diff --git a/clang/test/OpenMP/parallel_for_codegen.cpp b/clang/test/OpenMP/parallel_for_codegen.cpp
index 7f17f8c1d8553..a4270c6493b24 100644
--- a/clang/test/OpenMP/parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/parallel_for_codegen.cpp
@@ -298,7 +298,7 @@ void range_for_collapsed() {
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
@@ -1304,7 +1304,7 @@ void range_for_collapsed() {
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK1-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
@@ -1412,7 +1412,7 @@ void range_for_collapsed() {
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
@@ -2418,7 +2418,7 @@ void range_for_collapsed() {
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK2-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
@@ -2526,7 +2526,7 @@ void range_for_collapsed() {
// CHECK3-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
@@ -3532,7 +3532,7 @@ void range_for_collapsed() {
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK3-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
@@ -3640,7 +3640,7 @@ void range_for_collapsed() {
// CHECK4-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
@@ -4646,7 +4646,7 @@ void range_for_collapsed() {
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
-// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK4-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
@@ -4754,7 +4754,7 @@ void range_for_collapsed() {
// CHECK5-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]]
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG15]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8, !dbg [[DBG14]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1, !dbg [[DBG14]]
// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG14]]
// CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]]
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG14]]
@@ -5760,7 +5760,7 @@ void range_for_collapsed() {
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG111]]
// CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]], !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG111]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG111]]
// CHECK5-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]]
// CHECK5-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]], !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG111]]
@@ -5868,7 +5868,7 @@ void range_for_collapsed() {
// CHECK6-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64
// CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
@@ -6872,7 +6872,7 @@ void range_for_collapsed() {
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]]
// CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK6-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]]
-// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float
// CHECK6-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]]
// CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8
diff --git a/clang/test/OpenMP/parallel_master_codegen.cpp b/clang/test/OpenMP/parallel_master_codegen.cpp
index 46df40533cfcc..212fc8a6cc07e 100644
--- a/clang/test/OpenMP/parallel_master_codegen.cpp
+++ b/clang/test/OpenMP/parallel_master_codegen.cpp
@@ -559,9 +559,9 @@ void parallel_master_allocate() {
// CHECK13-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK13-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK13: omp_if.then:
-// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
-// CHECK13-NEXT: store i32 [[INC]], i32* [[CONV]], align 8
+// CHECK13-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK13-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK13-NEXT: br label [[OMP_IF_END]]
// CHECK13: omp_if.end:
@@ -597,9 +597,9 @@ void parallel_master_allocate() {
// CHECK14-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK14-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK14: omp_if.then:
-// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
-// CHECK14-NEXT: store i32 [[INC]], i32* [[CONV]], align 8
+// CHECK14-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK14-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK14-NEXT: br label [[OMP_IF_END]]
// CHECK14: omp_if.end:
@@ -658,9 +658,9 @@ void parallel_master_allocate() {
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK17-NEXT: store i32 [[ADD2]], i32* [[B]], align 4
-// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK17-NEXT: store i32 [[INC]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4
// CHECK17-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK17-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4
@@ -754,9 +754,9 @@ void parallel_master_allocate() {
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4
// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
// CHECK18-NEXT: store i32 [[ADD2]], i32* [[B]], align 4
-// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK18-NEXT: store i32 [[INC]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* @_ZN2St1yE, align 4
// CHECK18-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK18-NEXT: store i32 [[INC3]], i32* @_ZN2St1yE, align 4
@@ -827,9 +827,9 @@ void parallel_master_allocate() {
// CHECK21-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK21-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK21: omp_if.then:
-// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
-// CHECK21-NEXT: store i32 [[INC]], i32* [[CONV]], align 8
+// CHECK21-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK21-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK21-NEXT: br label [[OMP_IF_END]]
// CHECK21: omp_if.end:
@@ -865,9 +865,9 @@ void parallel_master_allocate() {
// CHECK22-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK22-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK22: omp_if.then:
-// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
-// CHECK22-NEXT: store i32 [[INC]], i32* [[CONV]], align 8
+// CHECK22-NEXT: store i32 [[INC]], i32* [[CONV]], align 4
// CHECK22-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
// CHECK22-NEXT: br label [[OMP_IF_END]]
// CHECK22: omp_if.end:
diff --git a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
index b0b1dfee02136..4fd6b958fd28a 100644
--- a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
+++ b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
@@ -139,7 +139,7 @@ struct S {
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then:
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
@@ -258,7 +258,7 @@ struct S {
// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then:
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
@@ -392,7 +392,7 @@ struct S {
// CHECK1-NEXT: store i32* [[TMP0]], i32** [[TMP6]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store i8*** [[TMP1]], i8**** [[TMP7]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_5]], align 4
@@ -430,7 +430,7 @@ struct S {
// CHECK1-NEXT: [[TMP23:%.*]] = load i8*, i8** [[TMP22]], align 8
// CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP23]], i8* align 8 [[TMP24]], i64 16, i1 false)
-// CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1
// CHECK1-NEXT: [[TMP26:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 5
@@ -824,7 +824,7 @@ struct S {
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
-// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK1-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
@@ -1065,7 +1065,7 @@ struct S {
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then:
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
@@ -1184,7 +1184,7 @@ struct S {
// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then:
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
@@ -1318,7 +1318,7 @@ struct S {
// CHECK2-NEXT: store i32* [[TMP0]], i32** [[TMP6]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store i8*** [[TMP1]], i8**** [[TMP7]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP0]], align 4
// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR_5]], align 4
@@ -1356,7 +1356,7 @@ struct S {
// CHECK2-NEXT: [[TMP23:%.*]] = load i8*, i8** [[TMP22]], align 8
// CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP23]], i8* align 8 [[TMP24]], i64 16, i1 false)
-// CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1
// CHECK2-NEXT: [[TMP26:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP21]], i32 0, i32 5
@@ -1750,7 +1750,7 @@ struct S {
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
-// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK2-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
index 2b3752cf01cdb..0c20823ba68fd 100644
--- a/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
+++ b/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
@@ -141,7 +141,7 @@ struct S {
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then:
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
@@ -260,7 +260,7 @@ struct S {
// CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK1: omp_if.then:
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
@@ -399,7 +399,7 @@ struct S {
// CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK1-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_5]], align 4
@@ -438,7 +438,7 @@ struct S {
// CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP25]], i8* align 8 [[TMP26]], i64 24, i1 false)
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP28]] to i1
// CHECK1-NEXT: [[TMP29:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 5
@@ -746,7 +746,7 @@ struct S {
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
-// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK1-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
@@ -986,7 +986,7 @@ struct S {
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then:
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
@@ -1105,7 +1105,7 @@ struct S {
// CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK2: omp_if.then:
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
@@ -1244,7 +1244,7 @@ struct S {
// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP8]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK2-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_5]], align 4
@@ -1283,7 +1283,7 @@ struct S {
// CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP25]], i8* align 8 [[TMP26]], i64 24, i1 false)
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP22]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP28:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP28]] to i1
// CHECK2-NEXT: [[TMP29:%.*]] = sext i1 [[TOBOOL]] to i32
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP23]], i32 0, i32 5
@@ -1571,7 +1571,7 @@ struct S {
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK2-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
-// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK2-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
@@ -1831,7 +1831,7 @@ struct S {
// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.then:
// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
@@ -1950,7 +1950,7 @@ struct S {
// CHECK3-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK3-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK3: omp_if.then:
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
@@ -2090,11 +2090,11 @@ struct S {
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK3-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 3
-// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[TMP10]], align 8
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_5]], align 4
@@ -2133,7 +2133,7 @@ struct S {
// CHECK3-NEXT: [[TMP28:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP27]], i8* align 8 [[TMP28]], i64 32, i1 false)
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL18:%.*]] = trunc i8 [[TMP30]] to i1
// CHECK3-NEXT: [[TMP31:%.*]] = sext i1 [[TOBOOL18]] to i32
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 5
@@ -2491,7 +2491,7 @@ struct S {
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK3-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
-// CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK3-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
@@ -2731,7 +2731,7 @@ struct S {
// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then:
// CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
-// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
@@ -2850,7 +2850,7 @@ struct S {
// CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
// CHECK4: omp_if.then:
-// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..4 to i32 (i32, i8*)*))
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates.1*
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], %struct.kmp_task_t_with_privates.1* [[TMP6]], i32 0, i32 0
@@ -2990,11 +2990,11 @@ struct S {
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 2
// CHECK4-NEXT: store i8*** [[TMP2]], i8**** [[TMP9]], align 8
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED]], i32 0, i32 3
-// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[TMP10]], align 8
-// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTCAPTURE_EXPR_5]], align 4
@@ -3033,7 +3033,7 @@ struct S {
// CHECK4-NEXT: [[TMP28:%.*]] = bitcast %struct.anon.2* [[AGG_CAPTURED]] to i8*
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP27]], i8* align 8 [[TMP28]], i64 32, i1 false)
// CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], %struct.kmp_task_t_with_privates.3* [[TMP24]], i32 0, i32 1
-// CHECK4-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP30:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL18:%.*]] = trunc i8 [[TMP30]] to i1
// CHECK4-NEXT: [[TMP31:%.*]] = sext i1 [[TOBOOL18]] to i32
// CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP25]], i32 0, i32 5
@@ -3391,7 +3391,7 @@ struct S {
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[AGG_CAPTURED]], i32 0, i32 1
// CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP7]], align 8
// CHECK4-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
-// CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
// CHECK4-NEXT: store i32* [[TMP]], i32** [[_TMP1]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4
diff --git a/clang/test/OpenMP/single_codegen.cpp b/clang/test/OpenMP/single_codegen.cpp
index a590aac9125d4..7cb75113c13a1 100644
--- a/clang/test/OpenMP/single_codegen.cpp
+++ b/clang/test/OpenMP/single_codegen.cpp
@@ -1031,9 +1031,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
-// CHECK1-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
@@ -1867,9 +1867,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK2-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
-// CHECK2-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
@@ -3049,9 +3049,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
-// CHECK3-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK3-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
@@ -3873,9 +3873,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4
-// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1
-// CHECK4-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8
+// CHECK4-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1
@@ -5053,9 +5053,9 @@ void array_func(int n, int a[n], St s[2]) {
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, !dbg [[DBG168:![0-9]+]]
// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1, !dbg [[DBG168]]
// CHECK5-NEXT: store i32 [[INC]], i32* [[TMP7]], align 4, !dbg [[DBG168]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 8, !dbg [[DBG169:![0-9]+]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV1]], align 4, !dbg [[DBG169:![0-9]+]]
// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1, !dbg [[DBG169]]
-// CHECK5-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8, !dbg [[DBG169]]
+// CHECK5-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 4, !dbg [[DBG169]]
// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP5]], align 8, !dbg [[DBG167]]
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG170:![0-9]+]]
// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG170]]
diff --git a/clang/test/OpenMP/target_codegen_global_capture.cpp b/clang/test/OpenMP/target_codegen_global_capture.cpp
index 3711603547762..ef41980136b8a 100644
--- a/clang/test/OpenMP/target_codegen_global_capture.cpp
+++ b/clang/test/OpenMP/target_codegen_global_capture.cpp
@@ -384,29 +384,29 @@ int tbar2(short a, short b, short c, short d){
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
-// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
+// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: land.lhs.true:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: land.lhs.true17:
-// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
@@ -697,29 +697,29 @@ int tbar2(short a, short b, short c, short d){
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
-// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
+// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: land.lhs.true:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: land.lhs.true17:
-// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
@@ -1029,29 +1029,29 @@ int tbar2(short a, short b, short c, short d){
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
-// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
+// CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: land.lhs.true:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK1: land.lhs.true17:
-// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
@@ -1326,29 +1326,29 @@ int tbar2(short a, short b, short c, short d){
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
+// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
-// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
+// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: land.lhs.true:
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: land.lhs.true17:
-// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
@@ -1639,29 +1639,29 @@ int tbar2(short a, short b, short c, short d){
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
+// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
-// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
+// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: land.lhs.true:
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: land.lhs.true17:
-// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
@@ -1971,29 +1971,29 @@ int tbar2(short a, short b, short c, short d){
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
+// CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
// CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
// CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
// CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
// CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
-// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
+// CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
// CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: land.lhs.true:
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 2
// CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
// CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
// CHECK2: land.lhs.true17:
-// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
// CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
@@ -2262,11 +2262,11 @@ int tbar2(short a, short b, short c, short d){
// CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
-// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
@@ -2279,7 +2279,7 @@ int tbar2(short a, short b, short c, short d){
// CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: land.lhs.true:
-// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
@@ -2569,11 +2569,11 @@ int tbar2(short a, short b, short c, short d){
// CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
-// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
@@ -2586,7 +2586,7 @@ int tbar2(short a, short b, short c, short d){
// CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: land.lhs.true:
-// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
@@ -2895,11 +2895,11 @@ int tbar2(short a, short b, short c, short d){
// CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
-// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
@@ -2912,7 +2912,7 @@ int tbar2(short a, short b, short c, short d){
// CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: land.lhs.true:
-// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
@@ -3186,11 +3186,11 @@ int tbar2(short a, short b, short c, short d){
// CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
-// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
@@ -3203,7 +3203,7 @@ int tbar2(short a, short b, short c, short d){
// CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: land.lhs.true:
-// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
+// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
@@ -3493,11 +3493,11 @@ int tbar2(short a, short b, short c, short d){
// CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
-// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
@@ -3510,7 +3510,7 @@ int tbar2(short a, short b, short c, short d){
// CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: land.lhs.true:
-// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
+// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
@@ -3819,11 +3819,11 @@ int tbar2(short a, short b, short c, short d){
// CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
// CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
// CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
-// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
// CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
// CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
// CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
@@ -3836,7 +3836,7 @@ int tbar2(short a, short b, short c, short d){
// CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
// CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: land.lhs.true:
-// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
+// CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
// CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
// CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp
index 012198a5ee7f1..bb478963849ac 100644
--- a/clang/test/OpenMP/target_parallel_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_codegen.cpp
@@ -594,7 +594,7 @@ int bar(int n){
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -612,9 +612,9 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -625,7 +625,7 @@ int bar(int n){
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -643,11 +643,11 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -671,11 +671,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -696,14 +696,14 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: ret void
//
//
@@ -738,7 +738,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -780,9 +780,9 @@ int bar(int n){
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -1137,7 +1137,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1167,7 +1167,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1202,15 +1202,15 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -1237,19 +1237,19 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -1271,11 +1271,11 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1299,14 +1299,14 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -1624,7 +1624,7 @@ int bar(int n){
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -1642,9 +1642,9 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void
//
//
@@ -1655,7 +1655,7 @@ int bar(int n){
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1673,11 +1673,11 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -1701,11 +1701,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1726,14 +1726,14 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: ret void
//
//
@@ -1768,7 +1768,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -1810,9 +1810,9 @@ int bar(int n){
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -2167,7 +2167,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2197,7 +2197,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2232,15 +2232,15 @@ int bar(int n){
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -2267,19 +2267,19 @@ int bar(int n){
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -2301,11 +2301,11 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2329,14 +2329,14 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -2679,7 +2679,7 @@ int bar(int n){
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -2697,11 +2697,11 @@ int bar(int n){
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -2727,7 +2727,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -2750,11 +2750,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: ret void
//
//
@@ -3246,11 +3246,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -3279,16 +3279,16 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -3312,7 +3312,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -3338,11 +3338,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -3685,7 +3685,7 @@ int bar(int n){
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -3703,11 +3703,11 @@ int bar(int n){
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -3733,7 +3733,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -3756,11 +3756,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: ret void
//
//
@@ -4252,11 +4252,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -4285,16 +4285,16 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -4318,7 +4318,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4344,11 +4344,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -4387,7 +4387,7 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -4405,11 +4405,11 @@ int bar(int n){
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -4433,11 +4433,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -4458,14 +4458,14 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: ret void
//
//
@@ -4500,7 +4500,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -4542,9 +4542,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -4599,15 +4599,15 @@ int bar(int n){
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -4634,19 +4634,19 @@ int bar(int n){
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -4673,7 +4673,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4703,7 +4703,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -4734,11 +4734,11 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -4762,14 +4762,14 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -4801,7 +4801,7 @@ int bar(int n){
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -4819,11 +4819,11 @@ int bar(int n){
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -4847,11 +4847,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -4872,14 +4872,14 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: ret void
//
//
@@ -4914,7 +4914,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -4956,9 +4956,9 @@ int bar(int n){
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -5013,15 +5013,15 @@ int bar(int n){
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -5048,19 +5048,19 @@ int bar(int n){
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -5087,7 +5087,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -5117,7 +5117,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -5148,11 +5148,11 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -5176,14 +5176,14 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -5215,7 +5215,7 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5233,11 +5233,11 @@ int bar(int n){
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -5263,7 +5263,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5286,11 +5286,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: ret void
//
//
@@ -5423,11 +5423,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -5456,16 +5456,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -5552,7 +5552,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5578,11 +5578,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -5614,7 +5614,7 @@ int bar(int n){
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5632,11 +5632,11 @@ int bar(int n){
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -5662,7 +5662,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5685,11 +5685,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: ret void
//
//
@@ -5822,11 +5822,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -5855,16 +5855,16 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -5951,7 +5951,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5977,11 +5977,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -6292,7 +6292,7 @@ int bar(int n){
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -6310,9 +6310,9 @@ int bar(int n){
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void
//
//
@@ -6323,7 +6323,7 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6341,11 +6341,11 @@ int bar(int n){
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -6369,11 +6369,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6394,14 +6394,14 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: ret void
//
//
@@ -6436,7 +6436,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -6478,9 +6478,9 @@ int bar(int n){
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -6835,7 +6835,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -6865,7 +6865,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -6900,15 +6900,15 @@ int bar(int n){
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -6935,19 +6935,19 @@ int bar(int n){
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -6969,11 +6969,11 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6997,14 +6997,14 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -7322,7 +7322,7 @@ int bar(int n){
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -7340,9 +7340,9 @@ int bar(int n){
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void
//
//
@@ -7353,7 +7353,7 @@ int bar(int n){
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7371,11 +7371,11 @@ int bar(int n){
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -7399,11 +7399,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7424,14 +7424,14 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: ret void
//
//
@@ -7466,7 +7466,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -7508,9 +7508,9 @@ int bar(int n){
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -7865,7 +7865,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -7895,7 +7895,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -7930,15 +7930,15 @@ int bar(int n){
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -7965,19 +7965,19 @@ int bar(int n){
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -7999,11 +7999,11 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8027,14 +8027,14 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -8377,7 +8377,7 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -8395,11 +8395,11 @@ int bar(int n){
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -8425,7 +8425,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -8448,11 +8448,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: ret void
//
//
@@ -8944,11 +8944,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -8977,16 +8977,16 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -9010,7 +9010,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9036,11 +9036,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -9383,7 +9383,7 @@ int bar(int n){
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9401,11 +9401,11 @@ int bar(int n){
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -9431,7 +9431,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9454,11 +9454,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: ret void
//
//
@@ -9950,11 +9950,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -9983,16 +9983,16 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -10016,7 +10016,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -10042,11 +10042,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -10085,7 +10085,7 @@ int bar(int n){
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10103,11 +10103,11 @@ int bar(int n){
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -10131,11 +10131,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10156,14 +10156,14 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: ret void
//
//
@@ -10198,7 +10198,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -10240,9 +10240,9 @@ int bar(int n){
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -10297,15 +10297,15 @@ int bar(int n){
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -10332,19 +10332,19 @@ int bar(int n){
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -10371,7 +10371,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -10401,7 +10401,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -10432,11 +10432,11 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10460,14 +10460,14 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -10499,7 +10499,7 @@ int bar(int n){
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10517,11 +10517,11 @@ int bar(int n){
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -10545,11 +10545,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10570,14 +10570,14 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: ret void
//
//
@@ -10612,7 +10612,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -10654,9 +10654,9 @@ int bar(int n){
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -10711,15 +10711,15 @@ int bar(int n){
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -10746,19 +10746,19 @@ int bar(int n){
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -10785,7 +10785,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -10815,7 +10815,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -10846,11 +10846,11 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10874,14 +10874,14 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -10913,7 +10913,7 @@ int bar(int n){
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -10931,11 +10931,11 @@ int bar(int n){
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -10961,7 +10961,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -10984,11 +10984,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: ret void
//
//
@@ -11121,11 +11121,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -11154,16 +11154,16 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -11250,7 +11250,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11276,11 +11276,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -11312,7 +11312,7 @@ int bar(int n){
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11330,11 +11330,11 @@ int bar(int n){
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
@@ -11360,7 +11360,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11383,11 +11383,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: ret void
//
//
@@ -11520,11 +11520,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -11553,16 +11553,16 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -11649,7 +11649,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11675,11 +11675,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
diff --git a/clang/test/OpenMP/target_parallel_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_debug_codegen.cpp
index 0ac82cb0106ca..f8cf931a431f8 100644
--- a/clang/test/OpenMP/target_parallel_debug_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_debug_codegen.cpp
@@ -246,7 +246,7 @@ int main() {
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG114]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG114]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG114]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG114]]
@@ -275,7 +275,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG123]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG123]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG123]]
// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG123]]
@@ -455,7 +455,7 @@ int main() {
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG191]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG191]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG191]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG191]]
@@ -485,7 +485,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG198]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG198]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG198]]
// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG198]]
diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp
index 585ecf61cf353..6ee0d4a6a8961 100644
--- a/clang/test/OpenMP/target_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp
@@ -735,7 +735,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -802,9 +802,9 @@ int bar(int n){
// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -844,15 +844,15 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -888,9 +888,9 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -942,11 +942,11 @@ int bar(int n){
// CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -964,9 +964,9 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK1: .omp.linear.pu:
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK1: .omp.linear.pu.done:
// CHECK1-NEXT: ret void
@@ -1088,11 +1088,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1152,14 +1152,14 @@ int bar(int n){
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1210,11 +1210,11 @@ int bar(int n){
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -1270,7 +1270,7 @@ int bar(int n){
// CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -1306,9 +1306,9 @@ int bar(int n){
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -1685,7 +1685,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1753,7 +1753,7 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1800,15 +1800,15 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -1854,11 +1854,11 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1920,14 +1920,14 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -2373,7 +2373,7 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2440,9 +2440,9 @@ int bar(int n){
// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2482,15 +2482,15 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2526,9 +2526,9 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -2580,11 +2580,11 @@ int bar(int n){
// CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2602,9 +2602,9 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK2: .omp.linear.pu:
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK2: .omp.linear.pu.done:
// CHECK2-NEXT: ret void
@@ -2726,11 +2726,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2790,14 +2790,14 @@ int bar(int n){
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2848,11 +2848,11 @@ int bar(int n){
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -2908,7 +2908,7 @@ int bar(int n){
// CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -2944,9 +2944,9 @@ int bar(int n){
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -3323,7 +3323,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3391,7 +3391,7 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3438,15 +3438,15 @@ int bar(int n){
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -3492,11 +3492,11 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -3558,14 +3558,14 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -4103,7 +4103,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4197,11 +4197,11 @@ int bar(int n){
// CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -4343,7 +4343,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4405,11 +4405,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -5040,11 +5040,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -5091,7 +5091,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5155,11 +5155,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -5697,7 +5697,7 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5791,11 +5791,11 @@ int bar(int n){
// CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -5937,7 +5937,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5999,11 +5999,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6634,11 +6634,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -6685,7 +6685,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6749,11 +6749,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -6879,15 +6879,15 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -6923,9 +6923,9 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -6977,11 +6977,11 @@ int bar(int n){
// CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6999,9 +6999,9 @@ int bar(int n){
// CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK9: .omp.linear.pu:
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK9: .omp.linear.pu.done:
// CHECK9-NEXT: ret void
@@ -7024,11 +7024,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7088,14 +7088,14 @@ int bar(int n){
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7146,11 +7146,11 @@ int bar(int n){
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -7206,7 +7206,7 @@ int bar(int n){
// CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -7242,9 +7242,9 @@ int bar(int n){
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -7321,15 +7321,15 @@ int bar(int n){
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -7380,7 +7380,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -7448,7 +7448,7 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -7491,11 +7491,11 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7557,14 +7557,14 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -7683,15 +7683,15 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -7727,9 +7727,9 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -7781,11 +7781,11 @@ int bar(int n){
// CHECK10-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK10-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK10-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7803,9 +7803,9 @@ int bar(int n){
// CHECK10-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK10: .omp.linear.pu:
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK10: .omp.linear.pu.done:
// CHECK10-NEXT: ret void
@@ -7828,11 +7828,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7892,14 +7892,14 @@ int bar(int n){
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK10-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK10-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7950,11 +7950,11 @@ int bar(int n){
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8010,7 +8010,7 @@ int bar(int n){
// CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -8046,9 +8046,9 @@ int bar(int n){
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK10-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -8125,15 +8125,15 @@ int bar(int n){
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -8184,7 +8184,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -8252,7 +8252,7 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -8295,11 +8295,11 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8361,14 +8361,14 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -8485,7 +8485,7 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -8579,11 +8579,11 @@ int bar(int n){
// CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8628,7 +8628,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -8690,11 +8690,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8916,11 +8916,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -9080,7 +9080,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9144,11 +9144,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -9265,7 +9265,7 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9359,11 +9359,11 @@ int bar(int n){
// CHECK12-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK12-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK12-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9408,7 +9408,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9470,11 +9470,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK12-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9696,11 +9696,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -9860,7 +9860,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9924,11 +9924,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -10367,7 +10367,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -10434,9 +10434,9 @@ int bar(int n){
// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
-// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -10476,15 +10476,15 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -10520,9 +10520,9 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -10574,11 +10574,11 @@ int bar(int n){
// CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -10596,9 +10596,9 @@ int bar(int n){
// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK17: .omp.linear.pu:
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK17: .omp.linear.pu.done:
// CHECK17-NEXT: ret void
@@ -10720,11 +10720,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10784,14 +10784,14 @@ int bar(int n){
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -10842,11 +10842,11 @@ int bar(int n){
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -10902,7 +10902,7 @@ int bar(int n){
// CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -10938,9 +10938,9 @@ int bar(int n){
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -11317,7 +11317,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -11385,7 +11385,7 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -11432,15 +11432,15 @@ int bar(int n){
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -11486,11 +11486,11 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -11552,14 +11552,14 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -12005,7 +12005,7 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -12072,9 +12072,9 @@ int bar(int n){
// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
-// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12114,15 +12114,15 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -12158,9 +12158,9 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -12212,11 +12212,11 @@ int bar(int n){
// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12234,9 +12234,9 @@ int bar(int n){
// CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK18: .omp.linear.pu:
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK18: .omp.linear.pu.done:
// CHECK18-NEXT: ret void
@@ -12358,11 +12358,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -12422,14 +12422,14 @@ int bar(int n){
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12480,11 +12480,11 @@ int bar(int n){
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -12540,7 +12540,7 @@ int bar(int n){
// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -12576,9 +12576,9 @@ int bar(int n){
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -12955,7 +12955,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -13023,7 +13023,7 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -13070,15 +13070,15 @@ int bar(int n){
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -13124,11 +13124,11 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13190,14 +13190,14 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -13735,7 +13735,7 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -13829,11 +13829,11 @@ int bar(int n){
// CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -13975,7 +13975,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14037,11 +14037,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -14672,11 +14672,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -14723,7 +14723,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14787,11 +14787,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -15329,7 +15329,7 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -15423,11 +15423,11 @@ int bar(int n){
// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -15569,7 +15569,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -15631,11 +15631,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -16266,11 +16266,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -16317,7 +16317,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -16381,11 +16381,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -16511,15 +16511,15 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -16555,9 +16555,9 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -16609,11 +16609,11 @@ int bar(int n){
// CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -16631,9 +16631,9 @@ int bar(int n){
// CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK25: .omp.linear.pu:
// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK25: .omp.linear.pu.done:
// CHECK25-NEXT: ret void
@@ -16656,11 +16656,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -16720,14 +16720,14 @@ int bar(int n){
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -16778,11 +16778,11 @@ int bar(int n){
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -16838,7 +16838,7 @@ int bar(int n){
// CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -16874,9 +16874,9 @@ int bar(int n){
// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -16953,15 +16953,15 @@ int bar(int n){
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -17012,7 +17012,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -17080,7 +17080,7 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -17123,11 +17123,11 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -17189,14 +17189,14 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -17315,15 +17315,15 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -17359,9 +17359,9 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -17413,11 +17413,11 @@ int bar(int n){
// CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
-// CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8
+// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -17435,9 +17435,9 @@ int bar(int n){
// CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK26: .omp.linear.pu:
// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK26: .omp.linear.pu.done:
// CHECK26-NEXT: ret void
@@ -17460,11 +17460,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -17524,14 +17524,14 @@ int bar(int n){
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -17582,11 +17582,11 @@ int bar(int n){
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -17642,7 +17642,7 @@ int bar(int n){
// CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -17678,9 +17678,9 @@ int bar(int n){
// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
-// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -17757,15 +17757,15 @@ int bar(int n){
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -17816,7 +17816,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -17884,7 +17884,7 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
-// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -17927,11 +17927,11 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -17993,14 +17993,14 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8
-// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -18117,7 +18117,7 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -18211,11 +18211,11 @@ int bar(int n){
// CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18260,7 +18260,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -18322,11 +18322,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18548,11 +18548,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -18712,7 +18712,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -18776,11 +18776,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -18897,7 +18897,7 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -18991,11 +18991,11 @@ int bar(int n){
// CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
-// CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19040,7 +19040,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19102,11 +19102,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19328,11 +19328,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -19492,7 +19492,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19556,11 +19556,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
diff --git a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp
index 7f9ba2c9e773d..b5a704c8f6d21 100644
--- a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp
@@ -316,7 +316,7 @@ int main() {
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG122]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG122]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG122]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG122]]
@@ -349,10 +349,10 @@ int main() {
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG132]]
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG132]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG132]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG132]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 8, !dbg [[DBG132]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1, !dbg [[DBG132]]
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG132]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG132]]
@@ -604,7 +604,7 @@ int main() {
// CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG213]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG213]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG213]]
// CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG213]]
@@ -634,7 +634,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG222]]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG222]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG222]]
// CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG222]]
diff --git a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
index d2529bb850263..475217fdc2c61 100644
--- a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
@@ -715,7 +715,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -782,9 +782,9 @@ int bar(int n){
// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -831,15 +831,15 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -875,9 +875,9 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -929,11 +929,11 @@ int bar(int n){
// CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
-// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -958,9 +958,9 @@ int bar(int n){
// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK1: .omp.linear.pu:
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK1: .omp.linear.pu.done:
// CHECK1-NEXT: ret void
@@ -977,11 +977,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1041,14 +1041,14 @@ int bar(int n){
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1106,11 +1106,11 @@ int bar(int n){
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -1166,7 +1166,7 @@ int bar(int n){
// CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -1202,9 +1202,9 @@ int bar(int n){
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -1588,7 +1588,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1656,7 +1656,7 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1710,15 +1710,15 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -1764,11 +1764,11 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1830,14 +1830,14 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41
-// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41
+// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !41
+// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41
+// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -2293,7 +2293,7 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2360,9 +2360,9 @@ int bar(int n){
// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2409,15 +2409,15 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2453,9 +2453,9 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -2507,11 +2507,11 @@ int bar(int n){
// CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
-// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2536,9 +2536,9 @@ int bar(int n){
// CHECK2-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK2: .omp.linear.pu:
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK2-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK2: .omp.linear.pu.done:
// CHECK2-NEXT: ret void
@@ -2555,11 +2555,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2619,14 +2619,14 @@ int bar(int n){
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2684,11 +2684,11 @@ int bar(int n){
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -2744,7 +2744,7 @@ int bar(int n){
// CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -2780,9 +2780,9 @@ int bar(int n){
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -3166,7 +3166,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3234,7 +3234,7 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3288,15 +3288,15 @@ int bar(int n){
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -3342,11 +3342,11 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -3408,14 +3408,14 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41
-// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41
+// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !41
+// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41
+// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !41
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -3970,7 +3970,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4064,11 +4064,11 @@ int bar(int n){
// CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
-// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -4114,7 +4114,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4176,11 +4176,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -4832,11 +4832,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -4883,7 +4883,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4947,11 +4947,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
-// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
+// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -5506,7 +5506,7 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5600,11 +5600,11 @@ int bar(int n){
// CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
-// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -5650,7 +5650,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5712,11 +5712,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6368,11 +6368,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -6419,7 +6419,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6483,11 +6483,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
-// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
+// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42
+// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -6943,7 +6943,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -7010,9 +7010,9 @@ int bar(int n){
// CHECK5-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK5-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7059,15 +7059,15 @@ int bar(int n){
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -7103,9 +7103,9 @@ int bar(int n){
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -7157,11 +7157,11 @@ int bar(int n){
// CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK5-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK5-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
-// CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7186,9 +7186,9 @@ int bar(int n){
// CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK5: .omp.linear.pu:
// CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK5-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK5-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK5: .omp.linear.pu.done:
// CHECK5-NEXT: ret void
@@ -7205,11 +7205,11 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7269,14 +7269,14 @@ int bar(int n){
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK5-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7334,11 +7334,11 @@ int bar(int n){
// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -7394,7 +7394,7 @@ int bar(int n){
// CHECK5-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -7430,9 +7430,9 @@ int bar(int n){
// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK5-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
-// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -7848,17 +7848,17 @@ int bar(int n){
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then:
@@ -7911,7 +7911,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then:
@@ -7942,7 +7942,7 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -7994,7 +7994,7 @@ int bar(int n){
// CHECK5-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK5-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK5-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
-// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -8052,15 +8052,15 @@ int bar(int n){
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -8106,11 +8106,11 @@ int bar(int n){
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8172,14 +8172,14 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
-// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
+// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -8635,7 +8635,7 @@ int bar(int n){
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -8702,9 +8702,9 @@ int bar(int n){
// CHECK6-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
// CHECK6-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
-// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8751,15 +8751,15 @@ int bar(int n){
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -8795,9 +8795,9 @@ int bar(int n){
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv()
// CHECK6-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -8849,11 +8849,11 @@ int bar(int n){
// CHECK6-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK6-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK6-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
-// CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK6-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8878,9 +8878,9 @@ int bar(int n){
// CHECK6-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK6: .omp.linear.pu:
// CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK6-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK6-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK6-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK6: .omp.linear.pu.done:
// CHECK6-NEXT: ret void
@@ -8897,11 +8897,11 @@ int bar(int n){
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8961,14 +8961,14 @@ int bar(int n){
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK6-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK6-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
-// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK6-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK6-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK6-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK6-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK6-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9026,11 +9026,11 @@ int bar(int n){
// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9086,7 +9086,7 @@ int bar(int n){
// CHECK6-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -9122,9 +9122,9 @@ int bar(int n){
// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK6-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
-// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK6-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK6-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -9540,17 +9540,17 @@ int bar(int n){
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK6-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then:
@@ -9603,7 +9603,7 @@ int bar(int n){
// CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then:
@@ -9634,7 +9634,7 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK6-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK6-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
-// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
+// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -9686,7 +9686,7 @@ int bar(int n){
// CHECK6-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK6-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK6-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
-// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK6-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -9744,15 +9744,15 @@ int bar(int n){
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK6-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -9798,11 +9798,11 @@ int bar(int n){
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9864,14 +9864,14 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
-// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
+// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
-// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
+// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -10426,7 +10426,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -10520,11 +10520,11 @@ int bar(int n){
// CHECK7-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK7-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK7-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
-// CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -10570,7 +10570,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -10632,11 +10632,11 @@ int bar(int n){
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK7-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK7-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -11201,13 +11201,13 @@ int bar(int n){
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK7: omp_if.then:
@@ -11259,7 +11259,7 @@ int bar(int n){
// CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK7: omp_if.then:
@@ -11402,11 +11402,11 @@ int bar(int n){
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -11453,7 +11453,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11517,11 +11517,11 @@ int bar(int n){
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
-// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -12076,7 +12076,7 @@ int bar(int n){
// CHECK8-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -12170,11 +12170,11 @@ int bar(int n){
// CHECK8-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK8-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK8-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
-// CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK8-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12220,7 +12220,7 @@ int bar(int n){
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -12282,11 +12282,11 @@ int bar(int n){
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK8-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK8-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK8-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK8-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK8-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12851,13 +12851,13 @@ int bar(int n){
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK8-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK8-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK8: omp_if.then:
@@ -12909,7 +12909,7 @@ int bar(int n){
// CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK8-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK8: omp_if.then:
@@ -13052,11 +13052,11 @@ int bar(int n){
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK8-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -13103,7 +13103,7 @@ int bar(int n){
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -13167,11 +13167,11 @@ int bar(int n){
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
-// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -17302,15 +17302,15 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -17346,9 +17346,9 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -17400,11 +17400,11 @@ int bar(int n){
// CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
-// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -17429,9 +17429,9 @@ int bar(int n){
// CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK17: .omp.linear.pu:
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK17: .omp.linear.pu.done:
// CHECK17-NEXT: ret void
@@ -17454,11 +17454,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -17518,14 +17518,14 @@ int bar(int n){
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
-// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
+// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -17583,11 +17583,11 @@ int bar(int n){
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -17643,7 +17643,7 @@ int bar(int n){
// CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -17679,9 +17679,9 @@ int bar(int n){
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -17765,15 +17765,15 @@ int bar(int n){
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -17824,7 +17824,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -17892,7 +17892,7 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -17942,11 +17942,11 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18008,14 +18008,14 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !29
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29
-// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29
+// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !29
+// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29
+// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -18131,15 +18131,15 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -18175,9 +18175,9 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -18229,11 +18229,11 @@ int bar(int n){
// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
-// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18258,9 +18258,9 @@ int bar(int n){
// CHECK18-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK18: .omp.linear.pu:
// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK18-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK18-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK18: .omp.linear.pu.done:
// CHECK18-NEXT: ret void
@@ -18283,11 +18283,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18347,14 +18347,14 @@ int bar(int n){
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
-// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
+// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18412,11 +18412,11 @@ int bar(int n){
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18472,7 +18472,7 @@ int bar(int n){
// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -18508,9 +18508,9 @@ int bar(int n){
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -18594,15 +18594,15 @@ int bar(int n){
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -18653,7 +18653,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -18721,7 +18721,7 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -18771,11 +18771,11 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18837,14 +18837,14 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
-// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29
+// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !29
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29
-// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29
+// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !29
+// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29
+// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !29
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -18958,7 +18958,7 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19052,11 +19052,11 @@ int bar(int n){
// CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
-// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19108,7 +19108,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19170,11 +19170,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
-// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19410,11 +19410,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -19581,7 +19581,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19645,11 +19645,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
-// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -19763,7 +19763,7 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19857,11 +19857,11 @@ int bar(int n){
// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
-// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19913,7 +19913,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19975,11 +19975,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
-// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -20215,11 +20215,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -20386,7 +20386,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -20450,11 +20450,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
-// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -20570,15 +20570,15 @@ int bar(int n){
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -20614,9 +20614,9 @@ int bar(int n){
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -20668,11 +20668,11 @@ int bar(int n){
// CHECK21-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK21-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK21-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
-// CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -20697,9 +20697,9 @@ int bar(int n){
// CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK21: .omp.linear.pu:
// CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK21-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK21-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK21-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK21-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK21: .omp.linear.pu.done:
// CHECK21-NEXT: ret void
@@ -20722,11 +20722,11 @@ int bar(int n){
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -20786,14 +20786,14 @@ int bar(int n){
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK21-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
-// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
+// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK21-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
-// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK21-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
+// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK21-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK21-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -20851,11 +20851,11 @@ int bar(int n){
// CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -20911,7 +20911,7 @@ int bar(int n){
// CHECK21-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -20947,9 +20947,9 @@ int bar(int n){
// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK21-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
-// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK21-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK21-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -21033,15 +21033,15 @@ int bar(int n){
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -21099,17 +21099,17 @@ int bar(int n){
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK21-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then:
@@ -21162,7 +21162,7 @@ int bar(int n){
// CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then:
@@ -21193,7 +21193,7 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
-// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -21245,7 +21245,7 @@ int bar(int n){
// CHECK21-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK21-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK21-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
-// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK21-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -21299,11 +21299,11 @@ int bar(int n){
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -21365,14 +21365,14 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK21-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
-// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -21488,15 +21488,15 @@ int bar(int n){
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
-// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -21532,9 +21532,9 @@ int bar(int n){
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
-// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
// CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
// CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
@@ -21586,11 +21586,11 @@ int bar(int n){
// CHECK22-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
// CHECK22-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
// CHECK22-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
-// CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK22-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
+// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -21615,9 +21615,9 @@ int bar(int n){
// CHECK22-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
// CHECK22: .omp.linear.pu:
// CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4
-// CHECK22-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 8
+// CHECK22-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4
// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4
-// CHECK22-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK22-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK22-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
// CHECK22: .omp.linear.pu.done:
// CHECK22-NEXT: ret void
@@ -21640,11 +21640,11 @@ int bar(int n){
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -21704,14 +21704,14 @@ int bar(int n){
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK22-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
// CHECK22-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
-// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
+// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20
// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK22-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
-// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK22-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20
+// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK22-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK22-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
-// CHECK22-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
+// CHECK22-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -21769,11 +21769,11 @@ int bar(int n){
// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK22-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21829,7 +21829,7 @@ int bar(int n){
// CHECK22-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -21865,9 +21865,9 @@ int bar(int n){
// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
// CHECK22-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
-// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK22-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
+// CHECK22-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
// CHECK22-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -21951,15 +21951,15 @@ int bar(int n){
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK22-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -22017,17 +22017,17 @@ int bar(int n){
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK22-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK22-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then:
@@ -22080,7 +22080,7 @@ int bar(int n){
// CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK22-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then:
@@ -22111,7 +22111,7 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK22-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
// CHECK22-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
-// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
+// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26
// CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -22163,7 +22163,7 @@ int bar(int n){
// CHECK22-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400
// CHECK22-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
// CHECK22-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8
-// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
// CHECK22-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
// CHECK22-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -22217,11 +22217,11 @@ int bar(int n){
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -22283,14 +22283,14 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
// CHECK22-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
-// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -22404,7 +22404,7 @@ int bar(int n){
// CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -22498,11 +22498,11 @@ int bar(int n){
// CHECK23-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK23-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK23-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
-// CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -22554,7 +22554,7 @@ int bar(int n){
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -22616,11 +22616,11 @@ int bar(int n){
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK23-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
-// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK23-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK23-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK23-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK23-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -22856,11 +22856,11 @@ int bar(int n){
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -22919,13 +22919,13 @@ int bar(int n){
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then:
@@ -22977,7 +22977,7 @@ int bar(int n){
// CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then:
@@ -23116,7 +23116,7 @@ int bar(int n){
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -23180,11 +23180,11 @@ int bar(int n){
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -23298,7 +23298,7 @@ int bar(int n){
// CHECK24-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
// CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -23392,11 +23392,11 @@ int bar(int n){
// CHECK24-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
// CHECK24-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
// CHECK24-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
-// CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK24-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
// CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
+// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -23448,7 +23448,7 @@ int bar(int n){
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -23510,11 +23510,11 @@ int bar(int n){
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK24-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
-// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK24-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK24-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK24-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
+// CHECK24-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -23750,11 +23750,11 @@ int bar(int n){
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK24-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -23813,13 +23813,13 @@ int bar(int n){
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK24-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then:
@@ -23871,7 +23871,7 @@ int bar(int n){
// CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
// CHECK24-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
// CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then:
@@ -24010,7 +24010,7 @@ int bar(int n){
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -24074,11 +24074,11 @@ int bar(int n){
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
diff --git a/clang/test/OpenMP/target_parallel_if_codegen.cpp b/clang/test/OpenMP/target_parallel_if_codegen.cpp
index 68590aeffcb55..750310cd908a8 100644
--- a/clang/test/OpenMP/target_parallel_if_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_if_codegen.cpp
@@ -498,11 +498,11 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -532,7 +532,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -552,7 +552,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -593,7 +593,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -647,7 +647,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -669,9 +669,9 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -686,11 +686,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -711,11 +711,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -1042,11 +1042,11 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -1076,7 +1076,7 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1096,7 +1096,7 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -1137,7 +1137,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -1191,7 +1191,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -1213,9 +1213,9 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void
//
//
@@ -1230,11 +1230,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1255,11 +1255,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void
//
//
@@ -1585,7 +1585,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -1634,7 +1634,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -1675,7 +1675,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -1767,7 +1767,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -1787,7 +1787,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2117,7 +2117,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -2166,7 +2166,7 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -2207,7 +2207,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -2299,7 +2299,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2319,7 +2319,7 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2343,7 +2343,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -2403,11 +2403,11 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -2437,7 +2437,7 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2457,7 +2457,7 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -2499,7 +2499,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2521,9 +2521,9 @@ int bar(int n){
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void
//
//
@@ -2538,11 +2538,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2563,11 +2563,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void
//
//
@@ -2580,7 +2580,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -2640,11 +2640,11 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -2674,7 +2674,7 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2694,7 +2694,7 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -2736,7 +2736,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2758,9 +2758,9 @@ int bar(int n){
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void
//
//
@@ -2775,11 +2775,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2800,11 +2800,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void
//
//
@@ -2817,7 +2817,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -2879,7 +2879,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -2928,7 +2928,7 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -3008,7 +3008,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -3028,7 +3028,7 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -3045,7 +3045,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -3107,7 +3107,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -3156,7 +3156,7 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -3236,7 +3236,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -3256,7 +3256,7 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -3580,11 +3580,11 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK17: omp_if.then:
@@ -3614,7 +3614,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3634,7 +3634,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK17: omp_if.then:
@@ -3675,7 +3675,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK17: omp_if.then:
@@ -3729,7 +3729,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -3751,9 +3751,9 @@ int bar(int n){
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void
//
//
@@ -3768,11 +3768,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3793,11 +3793,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void
//
//
@@ -4124,11 +4124,11 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK18: omp_if.then:
@@ -4158,7 +4158,7 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -4178,7 +4178,7 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK18: omp_if.then:
@@ -4219,7 +4219,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK18: omp_if.then:
@@ -4273,7 +4273,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -4295,9 +4295,9 @@ int bar(int n){
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void
//
//
@@ -4312,11 +4312,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4337,11 +4337,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void
//
//
@@ -4667,7 +4667,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK19: omp_if.then:
@@ -4716,7 +4716,7 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK19: omp_if.then:
@@ -4757,7 +4757,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK19: omp_if.then:
@@ -4849,7 +4849,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -4869,7 +4869,7 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -5199,7 +5199,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK20: omp_if.then:
@@ -5248,7 +5248,7 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK20: omp_if.then:
@@ -5289,7 +5289,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK20: omp_if.then:
@@ -5381,7 +5381,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -5401,7 +5401,7 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -5425,7 +5425,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK25: omp_if.then:
@@ -5485,11 +5485,11 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK25: omp_if.then:
@@ -5519,7 +5519,7 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -5539,7 +5539,7 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK25-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK25: omp_if.then:
@@ -5581,7 +5581,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -5603,9 +5603,9 @@ int bar(int n){
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void
//
//
@@ -5620,11 +5620,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -5645,11 +5645,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void
//
//
@@ -5662,7 +5662,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK26: omp_if.then:
@@ -5722,11 +5722,11 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK26: omp_if.then:
@@ -5756,7 +5756,7 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -5776,7 +5776,7 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK26-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK26: omp_if.then:
@@ -5818,7 +5818,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -5840,9 +5840,9 @@ int bar(int n){
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void
//
//
@@ -5857,11 +5857,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -5882,11 +5882,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void
//
//
@@ -5899,7 +5899,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK27: omp_if.then:
@@ -5961,7 +5961,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK27: omp_if.then:
@@ -6010,7 +6010,7 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK27-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK27: omp_if.then:
@@ -6090,7 +6090,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -6110,7 +6110,7 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -6127,7 +6127,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK28: omp_if.then:
@@ -6189,7 +6189,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK28: omp_if.then:
@@ -6238,7 +6238,7 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK28-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK28: omp_if.then:
@@ -6318,7 +6318,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -6338,7 +6338,7 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
diff --git a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
index ee15b339271d1..2c636c9187a19 100644
--- a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
@@ -465,9 +465,9 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -488,7 +488,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -530,7 +530,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void
@@ -553,7 +553,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void
@@ -603,14 +603,14 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -631,11 +631,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -922,9 +922,9 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -945,7 +945,7 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -987,7 +987,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void
@@ -1010,7 +1010,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void
@@ -1060,14 +1060,14 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1088,11 +1088,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void
//
//
@@ -1505,13 +1505,13 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -1531,7 +1531,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -1948,13 +1948,13 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -1974,7 +1974,7 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -1996,7 +1996,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void
@@ -2019,7 +2019,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void
@@ -2049,9 +2049,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2072,7 +2072,7 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2141,14 +2141,14 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2169,11 +2169,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void
//
//
@@ -2184,7 +2184,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void
@@ -2207,7 +2207,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void
@@ -2237,9 +2237,9 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2260,7 +2260,7 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2329,14 +2329,14 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2357,11 +2357,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void
//
//
@@ -2510,13 +2510,13 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2536,7 +2536,7 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2689,13 +2689,13 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2715,7 +2715,7 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2999,9 +2999,9 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3022,7 +3022,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3064,7 +3064,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void
@@ -3087,7 +3087,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void
@@ -3137,14 +3137,14 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3165,11 +3165,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void
//
//
@@ -3456,9 +3456,9 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3479,7 +3479,7 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3521,7 +3521,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void
@@ -3544,7 +3544,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void
@@ -3594,14 +3594,14 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3622,11 +3622,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void
//
//
@@ -4039,13 +4039,13 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -4065,7 +4065,7 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -4482,13 +4482,13 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -4508,7 +4508,7 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -4530,7 +4530,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void
@@ -4553,7 +4553,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void
@@ -4583,9 +4583,9 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4606,7 +4606,7 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -4675,14 +4675,14 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4703,11 +4703,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void
//
//
@@ -4718,7 +4718,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void
@@ -4741,7 +4741,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void
@@ -4771,9 +4771,9 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4794,7 +4794,7 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -4863,14 +4863,14 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4891,11 +4891,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void
//
//
@@ -5044,13 +5044,13 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -5070,7 +5070,7 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -5223,13 +5223,13 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]])
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -5249,7 +5249,7 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp
index 387be05f7bc04..7b3a3d8251544 100644
--- a/clang/test/OpenMP/target_teams_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_codegen.cpp
@@ -684,10 +684,10 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -822,7 +822,7 @@ int bar(int n){
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -840,9 +840,9 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -853,7 +853,7 @@ int bar(int n){
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -871,11 +871,11 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK1-NEXT: ret void
//
//
@@ -890,11 +890,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -915,14 +915,14 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: ret void
//
//
@@ -957,7 +957,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -999,9 +999,9 @@ int bar(int n){
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -1045,7 +1045,7 @@ int bar(int n){
// CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -1064,7 +1064,7 @@ int bar(int n){
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -1092,7 +1092,7 @@ int bar(int n){
// CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -1501,7 +1501,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1531,7 +1531,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1566,15 +1566,15 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -1601,19 +1601,19 @@ int bar(int n){
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -1635,11 +1635,11 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1663,14 +1663,14 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -2067,10 +2067,10 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2205,7 +2205,7 @@ int bar(int n){
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2223,9 +2223,9 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void
//
//
@@ -2236,7 +2236,7 @@ int bar(int n){
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2254,11 +2254,11 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK2-NEXT: ret void
//
//
@@ -2273,11 +2273,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2298,14 +2298,14 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: ret void
//
//
@@ -2340,7 +2340,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2382,9 +2382,9 @@ int bar(int n){
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -2428,7 +2428,7 @@ int bar(int n){
// CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -2447,7 +2447,7 @@ int bar(int n){
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -2475,7 +2475,7 @@ int bar(int n){
// CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -2884,7 +2884,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2914,7 +2914,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2949,15 +2949,15 @@ int bar(int n){
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -2984,19 +2984,19 @@ int bar(int n){
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -3018,11 +3018,11 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -3046,14 +3046,14 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -3444,7 +3444,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -3605,7 +3605,7 @@ int bar(int n){
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -3623,11 +3623,11 @@ int bar(int n){
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK3-NEXT: ret void
//
//
@@ -3644,7 +3644,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -3667,11 +3667,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: ret void
//
//
@@ -4299,11 +4299,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -4332,16 +4332,16 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -4365,7 +4365,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4391,11 +4391,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -4786,7 +4786,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4947,7 +4947,7 @@ int bar(int n){
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4965,11 +4965,11 @@ int bar(int n){
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK4-NEXT: ret void
//
//
@@ -4986,7 +4986,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5009,11 +5009,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: ret void
//
//
@@ -5641,11 +5641,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -5674,16 +5674,16 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -5707,7 +5707,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5733,11 +5733,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -5766,10 +5766,10 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -5797,7 +5797,7 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -5815,11 +5815,11 @@ int bar(int n){
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK9-NEXT: ret void
//
//
@@ -5834,11 +5834,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -5859,14 +5859,14 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: ret void
//
//
@@ -5901,7 +5901,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -5943,9 +5943,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -5989,7 +5989,7 @@ int bar(int n){
// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -6008,7 +6008,7 @@ int bar(int n){
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -6036,7 +6036,7 @@ int bar(int n){
// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -6113,15 +6113,15 @@ int bar(int n){
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -6148,19 +6148,19 @@ int bar(int n){
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -6187,7 +6187,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -6217,7 +6217,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -6248,11 +6248,11 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6276,14 +6276,14 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -6305,10 +6305,10 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6336,7 +6336,7 @@ int bar(int n){
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6354,11 +6354,11 @@ int bar(int n){
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK10-NEXT: ret void
//
//
@@ -6373,11 +6373,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6398,14 +6398,14 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: ret void
//
//
@@ -6440,7 +6440,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -6482,9 +6482,9 @@ int bar(int n){
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -6528,7 +6528,7 @@ int bar(int n){
// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -6547,7 +6547,7 @@ int bar(int n){
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -6575,7 +6575,7 @@ int bar(int n){
// CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -6652,15 +6652,15 @@ int bar(int n){
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -6687,19 +6687,19 @@ int bar(int n){
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -6726,7 +6726,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -6756,7 +6756,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -6787,11 +6787,11 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -6815,14 +6815,14 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -6845,7 +6845,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6873,7 +6873,7 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6891,11 +6891,11 @@ int bar(int n){
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK11-NEXT: ret void
//
//
@@ -6912,7 +6912,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6935,11 +6935,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: ret void
//
//
@@ -7177,11 +7177,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -7210,16 +7210,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -7306,7 +7306,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -7332,11 +7332,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -7359,7 +7359,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -7387,7 +7387,7 @@ int bar(int n){
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -7405,11 +7405,11 @@ int bar(int n){
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK12-NEXT: ret void
//
//
@@ -7426,7 +7426,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -7449,11 +7449,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: ret void
//
//
@@ -7691,11 +7691,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -7724,16 +7724,16 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -7820,7 +7820,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -7846,11 +7846,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -8240,10 +8240,10 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8378,7 +8378,7 @@ int bar(int n){
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -8396,9 +8396,9 @@ int bar(int n){
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void
//
//
@@ -8409,7 +8409,7 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8427,11 +8427,11 @@ int bar(int n){
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK17-NEXT: ret void
//
//
@@ -8446,11 +8446,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8471,14 +8471,14 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: ret void
//
//
@@ -8513,7 +8513,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -8555,9 +8555,9 @@ int bar(int n){
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -8601,7 +8601,7 @@ int bar(int n){
// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -8620,7 +8620,7 @@ int bar(int n){
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -8648,7 +8648,7 @@ int bar(int n){
// CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -9057,7 +9057,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -9087,7 +9087,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -9122,15 +9122,15 @@ int bar(int n){
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -9157,19 +9157,19 @@ int bar(int n){
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -9191,11 +9191,11 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9219,14 +9219,14 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -9623,10 +9623,10 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9761,7 +9761,7 @@ int bar(int n){
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -9779,9 +9779,9 @@ int bar(int n){
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void
//
//
@@ -9792,7 +9792,7 @@ int bar(int n){
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9810,11 +9810,11 @@ int bar(int n){
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK18-NEXT: ret void
//
//
@@ -9829,11 +9829,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9854,14 +9854,14 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: ret void
//
//
@@ -9896,7 +9896,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -9938,9 +9938,9 @@ int bar(int n){
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -9984,7 +9984,7 @@ int bar(int n){
// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -10003,7 +10003,7 @@ int bar(int n){
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -10031,7 +10031,7 @@ int bar(int n){
// CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -10440,7 +10440,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -10470,7 +10470,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -10505,15 +10505,15 @@ int bar(int n){
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -10540,19 +10540,19 @@ int bar(int n){
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -10574,11 +10574,11 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10602,14 +10602,14 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -11000,7 +11000,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11161,7 +11161,7 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11179,11 +11179,11 @@ int bar(int n){
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK19-NEXT: ret void
//
//
@@ -11200,7 +11200,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11223,11 +11223,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: ret void
//
//
@@ -11855,11 +11855,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -11888,16 +11888,16 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -11921,7 +11921,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11947,11 +11947,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -12342,7 +12342,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -12503,7 +12503,7 @@ int bar(int n){
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -12521,11 +12521,11 @@ int bar(int n){
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK20-NEXT: ret void
//
//
@@ -12542,7 +12542,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -12565,11 +12565,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: ret void
//
//
@@ -13197,11 +13197,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -13230,16 +13230,16 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -13263,7 +13263,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -13289,11 +13289,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -13322,10 +13322,10 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13353,7 +13353,7 @@ int bar(int n){
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13371,11 +13371,11 @@ int bar(int n){
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK25-NEXT: ret void
//
//
@@ -13390,11 +13390,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13415,14 +13415,14 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: ret void
//
//
@@ -13457,7 +13457,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -13499,9 +13499,9 @@ int bar(int n){
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -13545,7 +13545,7 @@ int bar(int n){
// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -13564,7 +13564,7 @@ int bar(int n){
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -13592,7 +13592,7 @@ int bar(int n){
// CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -13669,15 +13669,15 @@ int bar(int n){
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -13704,19 +13704,19 @@ int bar(int n){
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -13743,7 +13743,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -13773,7 +13773,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -13804,11 +13804,11 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13832,14 +13832,14 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -13861,10 +13861,10 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13892,7 +13892,7 @@ int bar(int n){
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13910,11 +13910,11 @@ int bar(int n){
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
+// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK26-NEXT: ret void
//
//
@@ -13929,11 +13929,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13954,14 +13954,14 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: ret void
//
//
@@ -13996,7 +13996,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -14038,9 +14038,9 @@ int bar(int n){
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double
@@ -14084,7 +14084,7 @@ int bar(int n){
// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -14103,7 +14103,7 @@ int bar(int n){
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -14131,7 +14131,7 @@ int bar(int n){
// CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8
@@ -14208,15 +14208,15 @@ int bar(int n){
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -14243,19 +14243,19 @@ int bar(int n){
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
+// CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2
+// CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1
// CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
-// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8
+// CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
@@ -14282,7 +14282,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -14312,7 +14312,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -14343,11 +14343,11 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -14371,14 +14371,14 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
@@ -14401,7 +14401,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14429,7 +14429,7 @@ int bar(int n){
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14447,11 +14447,11 @@ int bar(int n){
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK27-NEXT: ret void
//
//
@@ -14468,7 +14468,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14491,11 +14491,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: ret void
//
//
@@ -14733,11 +14733,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -14766,16 +14766,16 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -14862,7 +14862,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14888,11 +14888,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
@@ -14915,7 +14915,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14943,7 +14943,7 @@ int bar(int n){
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14961,11 +14961,11 @@ int bar(int n){
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2
// CHECK28-NEXT: ret void
//
//
@@ -14982,7 +14982,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -15005,11 +15005,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: ret void
//
//
@@ -15247,11 +15247,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -15280,16 +15280,16 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
+// CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
// CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
-// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4
+// CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
@@ -15376,7 +15376,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -15402,11 +15402,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp
index 63e5e4dc10ef5..300caa04c22d4 100644
--- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp
@@ -648,10 +648,10 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -837,7 +837,7 @@ int bar(int n){
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -893,9 +893,9 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -918,7 +918,7 @@ int bar(int n){
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -974,11 +974,11 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1005,11 +1005,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1068,14 +1068,14 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1126,11 +1126,11 @@ int bar(int n){
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -1186,7 +1186,7 @@ int bar(int n){
// CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -1221,9 +1221,9 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK1-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK1-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -1637,7 +1637,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1705,7 +1705,7 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1756,19 +1756,19 @@ int bar(int n){
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -1809,9 +1809,9 @@ int bar(int n){
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -1864,19 +1864,19 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -1914,11 +1914,11 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1980,14 +1980,14 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -2368,10 +2368,10 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2557,7 +2557,7 @@ int bar(int n){
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2613,9 +2613,9 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK2-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2638,7 +2638,7 @@ int bar(int n){
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2694,11 +2694,11 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2725,11 +2725,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2788,14 +2788,14 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2846,11 +2846,11 @@ int bar(int n){
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -2906,7 +2906,7 @@ int bar(int n){
// CHECK2-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -2941,9 +2941,9 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK2-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK2-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -3357,7 +3357,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3425,7 +3425,7 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3476,19 +3476,19 @@ int bar(int n){
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -3529,9 +3529,9 @@ int bar(int n){
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -3584,19 +3584,19 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK2-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK2-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK2-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -3634,11 +3634,11 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -3700,14 +3700,14 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -4083,7 +4083,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4345,7 +4345,7 @@ int bar(int n){
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4401,11 +4401,11 @@ int bar(int n){
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -4434,7 +4434,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4495,11 +4495,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -5171,11 +5171,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -5272,16 +5272,16 @@ int bar(int n){
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -5321,7 +5321,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5385,11 +5385,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -5765,7 +5765,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6027,7 +6027,7 @@ int bar(int n){
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6083,11 +6083,11 @@ int bar(int n){
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6116,7 +6116,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6177,11 +6177,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6853,11 +6853,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -6954,16 +6954,16 @@ int bar(int n){
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK4-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK4-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -7003,7 +7003,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -7067,11 +7067,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -7112,10 +7112,10 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7193,7 +7193,7 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7249,11 +7249,11 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7280,11 +7280,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7343,14 +7343,14 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7401,11 +7401,11 @@ int bar(int n){
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -7461,7 +7461,7 @@ int bar(int n){
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -7496,9 +7496,9 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
-// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -7579,19 +7579,19 @@ int bar(int n){
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK9-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -7632,9 +7632,9 @@ int bar(int n){
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -7687,19 +7687,19 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK9-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK9-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK9-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK9-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK9-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK9-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK9-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK9-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK9-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK9-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -7742,7 +7742,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -7810,7 +7810,7 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK9-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -7853,11 +7853,11 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7919,14 +7919,14 @@ int bar(int n){
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -7960,10 +7960,10 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8041,7 +8041,7 @@ int bar(int n){
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8097,11 +8097,11 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK10-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8128,11 +8128,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8191,14 +8191,14 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8249,11 +8249,11 @@ int bar(int n){
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8309,7 +8309,7 @@ int bar(int n){
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -8344,9 +8344,9 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
-// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -8427,19 +8427,19 @@ int bar(int n){
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK10-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK10-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -8480,9 +8480,9 @@ int bar(int n){
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -8535,19 +8535,19 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK10-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK10-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK10-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK10-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK10-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK10-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK10-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK10-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK10-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK10-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK10-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK10-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK10-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -8590,7 +8590,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -8658,7 +8658,7 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK10-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -8701,11 +8701,11 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8767,14 +8767,14 @@ int bar(int n){
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -8809,7 +8809,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -8887,7 +8887,7 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -8943,11 +8943,11 @@ int bar(int n){
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8976,7 +8976,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9037,11 +9037,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9268,11 +9268,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK11-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -9369,16 +9369,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK11-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK11-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK11-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK11-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK11-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -9531,7 +9531,7 @@ int bar(int n){
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9595,11 +9595,11 @@ int bar(int n){
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -9634,7 +9634,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9712,7 +9712,7 @@ int bar(int n){
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9768,11 +9768,11 @@ int bar(int n){
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK12-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9801,7 +9801,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -9862,11 +9862,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -10093,11 +10093,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK12-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK12-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK12-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -10194,16 +10194,16 @@ int bar(int n){
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK12-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK12-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK12-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK12-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK12-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK12-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK12-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK12-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -10356,7 +10356,7 @@ int bar(int n){
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -10420,11 +10420,11 @@ int bar(int n){
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -10798,10 +10798,10 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10987,7 +10987,7 @@ int bar(int n){
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -11043,9 +11043,9 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK17-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -11068,7 +11068,7 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -11124,11 +11124,11 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -11155,11 +11155,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -11218,14 +11218,14 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -11276,11 +11276,11 @@ int bar(int n){
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11336,7 +11336,7 @@ int bar(int n){
// CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -11371,9 +11371,9 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -11787,7 +11787,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -11855,7 +11855,7 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -11906,19 +11906,19 @@ int bar(int n){
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -11959,9 +11959,9 @@ int bar(int n){
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -12014,19 +12014,19 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -12064,11 +12064,11 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -12130,14 +12130,14 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -12518,10 +12518,10 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -12707,7 +12707,7 @@ int bar(int n){
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -12763,9 +12763,9 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK18-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12788,7 +12788,7 @@ int bar(int n){
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -12844,11 +12844,11 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12875,11 +12875,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -12938,14 +12938,14 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12996,11 +12996,11 @@ int bar(int n){
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -13056,7 +13056,7 @@ int bar(int n){
// CHECK18-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -13091,9 +13091,9 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -13507,7 +13507,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -13575,7 +13575,7 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -13626,19 +13626,19 @@ int bar(int n){
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -13679,9 +13679,9 @@ int bar(int n){
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -13734,19 +13734,19 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -13784,11 +13784,11 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -13850,14 +13850,14 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -14233,7 +14233,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14495,7 +14495,7 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14551,11 +14551,11 @@ int bar(int n){
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -14584,7 +14584,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14645,11 +14645,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -15321,11 +15321,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -15422,16 +15422,16 @@ int bar(int n){
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -15471,7 +15471,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -15535,11 +15535,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -15915,7 +15915,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -16177,7 +16177,7 @@ int bar(int n){
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -16233,11 +16233,11 @@ int bar(int n){
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -16266,7 +16266,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -16327,11 +16327,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -17003,11 +17003,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -17104,16 +17104,16 @@ int bar(int n){
// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -17153,7 +17153,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -17217,11 +17217,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -17262,10 +17262,10 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -17343,7 +17343,7 @@ int bar(int n){
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -17399,11 +17399,11 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK25-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -17430,11 +17430,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -17493,14 +17493,14 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK25: omp.body.continue:
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -17551,11 +17551,11 @@ int bar(int n){
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -17611,7 +17611,7 @@ int bar(int n){
// CHECK25-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -17646,9 +17646,9 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
-// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -17729,19 +17729,19 @@ int bar(int n){
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK25-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK25-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK25-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -17782,9 +17782,9 @@ int bar(int n){
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -17837,19 +17837,19 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK25-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK25-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK25-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK25-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK25-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK25-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK25-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK25-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK25-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK25-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK25-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK25-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK25-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -17892,7 +17892,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -17960,7 +17960,7 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK25-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -18003,11 +18003,11 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18069,14 +18069,14 @@ int bar(int n){
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -18110,10 +18110,10 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18191,7 +18191,7 @@ int bar(int n){
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18247,11 +18247,11 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK26-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8
+// CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18278,11 +18278,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18341,14 +18341,14 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK26: omp.body.continue:
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18399,11 +18399,11 @@ int bar(int n){
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18459,7 +18459,7 @@ int bar(int n){
// CHECK26-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
@@ -18494,9 +18494,9 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
-// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13
// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
@@ -18577,19 +18577,19 @@ int bar(int n){
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK26-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK26-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK26-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -18630,9 +18630,9 @@ int bar(int n){
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -18685,19 +18685,19 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK26-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK26-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4
-// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK26-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 8
-// CHECK26-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK26-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4
+// CHECK26-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8
-// CHECK26-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2
+// CHECK26-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK26-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK26-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK26-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK26-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8
+// CHECK26-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -18740,7 +18740,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -18808,7 +18808,7 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK26-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -18851,11 +18851,11 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18917,14 +18917,14 @@ int bar(int n){
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8
+// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -18959,7 +18959,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19037,7 +19037,7 @@ int bar(int n){
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19093,11 +19093,11 @@ int bar(int n){
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK27-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19126,7 +19126,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19187,11 +19187,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK27: omp.body.continue:
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19418,11 +19418,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK27-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK27-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK27-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -19519,16 +19519,16 @@ int bar(int n){
// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK27-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK27-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK27-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK27-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK27-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK27-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK27-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK27-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -19681,7 +19681,7 @@ int bar(int n){
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19745,11 +19745,11 @@ int bar(int n){
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -19784,7 +19784,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19862,7 +19862,7 @@ int bar(int n){
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -19918,11 +19918,11 @@ int bar(int n){
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK28-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19951,7 +19951,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -20012,11 +20012,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK28: omp.body.continue:
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -20243,11 +20243,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK28-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK28-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK28-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -20344,16 +20344,16 @@ int bar(int n){
// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK28-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4
-// CHECK28-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
+// CHECK28-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK28-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK28-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK28-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK28-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4
+// CHECK28-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -20506,7 +20506,7 @@ int bar(int n){
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -20570,11 +20570,11 @@ int bar(int n){
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
-// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4
+// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
diff --git a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp
index fcb73beed6eda..e5b6eac75b0d9 100644
--- a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp
@@ -820,11 +820,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -868,9 +868,9 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -1264,11 +1264,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1312,9 +1312,9 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
diff --git a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp
index 8a278c56a29e0..6022cf67baf24 100644
--- a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp
@@ -1755,7 +1755,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1789,7 +1789,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -1871,7 +1871,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1905,7 +1905,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -1991,11 +1991,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -2032,7 +2032,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2049,7 +2049,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -2700,7 +2700,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2734,7 +2734,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2816,7 +2816,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2850,7 +2850,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2936,11 +2936,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -2977,7 +2977,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2994,7 +2994,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
diff --git a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
index 106500b00271a..3af5b56cf7edb 100644
--- a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
@@ -345,11 +345,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -446,7 +446,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -458,9 +458,9 @@ int main() {
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -694,7 +694,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -794,7 +794,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1135,11 +1135,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1236,7 +1236,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1248,9 +1248,9 @@ int main() {
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1484,7 +1484,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1584,7 +1584,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -3407,7 +3407,7 @@ int main() {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -3416,7 +3416,7 @@ int main() {
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -3481,10 +3481,10 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
-// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -3664,7 +3664,7 @@ int main() {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -3673,7 +3673,7 @@ int main() {
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -3738,10 +3738,10 @@ int main() {
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
-// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp
index a1087d5a98437..51e4b21eb6c64 100644
--- a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp
@@ -182,11 +182,11 @@ int main() {
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -298,9 +298,9 @@ int main() {
// CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[TMP19]], align 8
// CHECK1-NEXT: store volatile double [[TMP20]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK1-NEXT: store float [[TMP22]], float* [[CONV3]], align 8
+// CHECK1-NEXT: store float [[TMP22]], float* [[CONV3]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void
@@ -361,11 +361,11 @@ int main() {
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -477,9 +477,9 @@ int main() {
// CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[TMP19]], align 8
// CHECK2-NEXT: store volatile double [[TMP20]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 8
+// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK2-NEXT: store float [[TMP22]], float* [[CONV3]], align 8
+// CHECK2-NEXT: store float [[TMP22]], float* [[CONV3]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void
@@ -977,12 +977,12 @@ int main() {
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -1104,7 +1104,7 @@ int main() {
// CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
@@ -1129,7 +1129,7 @@ int main() {
// CHECK9-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 4
// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK9: .omp.lastprivate.done:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
@@ -1320,7 +1320,7 @@ int main() {
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1439,7 +1439,7 @@ int main() {
// CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
@@ -1683,12 +1683,12 @@ int main() {
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -1810,7 +1810,7 @@ int main() {
// CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
@@ -1835,7 +1835,7 @@ int main() {
// CHECK10-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP30]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 4
// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK10: .omp.lastprivate.done:
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
@@ -2026,7 +2026,7 @@ int main() {
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2145,7 +2145,7 @@ int main() {
// CHECK10-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 8, i1 false)
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
index 1b0bd4615118e..2148b693e151a 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
@@ -136,10 +136,10 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -171,7 +171,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -217,7 +217,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -267,7 +267,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -369,7 +369,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -404,7 +404,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -450,7 +450,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -503,7 +503,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -754,10 +754,10 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -789,7 +789,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -835,7 +835,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -885,7 +885,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -987,7 +987,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1022,7 +1022,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1068,7 +1068,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1121,7 +1121,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1379,10 +1379,10 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK3-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1414,7 +1414,7 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1460,7 +1460,7 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1510,7 +1510,7 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1612,7 +1612,7 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1647,7 +1647,7 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1693,7 +1693,7 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1746,7 +1746,7 @@ int target_teams_fun(int *g){
// CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3046,10 +3046,10 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3081,7 +3081,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3127,7 +3127,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3177,7 +3177,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3279,7 +3279,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3314,7 +3314,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3360,7 +3360,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3413,7 +3413,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3508,10 +3508,10 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK11-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3543,7 +3543,7 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3589,7 +3589,7 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3639,7 +3639,7 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3741,7 +3741,7 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3776,7 +3776,7 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3822,7 +3822,7 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4
// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3875,7 +3875,7 @@ int target_teams_fun(int *g){
// CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
index f2b302b1f9f1b..281654218d09c 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
@@ -1117,11 +1117,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1167,9 +1167,9 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -1224,11 +1224,11 @@ int main (int argc, char **argv) {
// CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
-// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4
// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1291,9 +1291,9 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -1766,11 +1766,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1816,9 +1816,9 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -1873,11 +1873,11 @@ int main (int argc, char **argv) {
// CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8
-// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4
// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1940,9 +1940,9 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
index 48bdd180c93d3..23e40d279777e 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
@@ -2633,7 +2633,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2668,7 +2668,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2714,7 +2714,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2767,7 +2767,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2855,7 +2855,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2890,7 +2890,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2936,7 +2936,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2989,7 +2989,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3081,11 +3081,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -3124,7 +3124,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3141,7 +3141,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -3172,11 +3172,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -3255,7 +3255,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3733,7 +3733,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -3766,7 +3766,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -3793,7 +3793,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -4173,7 +4173,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4208,7 +4208,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -4254,7 +4254,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4307,7 +4307,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -4395,7 +4395,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4430,7 +4430,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -4476,7 +4476,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4529,7 +4529,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -4621,11 +4621,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -4664,7 +4664,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -4681,7 +4681,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -4712,11 +4712,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -4795,7 +4795,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -5273,7 +5273,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -5306,7 +5306,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -5333,7 +5333,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
index 1eb2cdd9018eb..643cdf2cd3750 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
@@ -406,11 +406,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -509,11 +509,11 @@ int main() {
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -677,7 +677,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -689,9 +689,9 @@ int main() {
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -892,7 +892,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -993,7 +993,7 @@ int main() {
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1140,7 +1140,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1468,11 +1468,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1571,11 +1571,11 @@ int main() {
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1739,7 +1739,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1751,9 +1751,9 @@ int main() {
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1954,7 +1954,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2055,7 +2055,7 @@ int main() {
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2202,7 +2202,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -4528,7 +4528,7 @@ int main() {
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4537,7 +4537,7 @@ int main() {
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4604,7 +4604,7 @@ int main() {
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4613,7 +4613,7 @@ int main() {
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4699,10 +4699,10 @@ int main() {
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
-// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -4882,7 +4882,7 @@ int main() {
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4891,7 +4891,7 @@ int main() {
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4958,7 +4958,7 @@ int main() {
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4967,7 +4967,7 @@ int main() {
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5053,10 +5053,10 @@ int main() {
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
-// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -5116,11 +5116,11 @@ int main() {
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5219,11 +5219,11 @@ int main() {
// CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5387,7 +5387,7 @@ int main() {
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -5399,9 +5399,9 @@ int main() {
// CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
-// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
+// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK13: omp.body.continue:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -5458,7 +5458,7 @@ int main() {
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -5559,7 +5559,7 @@ int main() {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -5706,7 +5706,7 @@ int main() {
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -5855,11 +5855,11 @@ int main() {
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5958,11 +5958,11 @@ int main() {
// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -6126,7 +6126,7 @@ int main() {
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -6138,9 +6138,9 @@ int main() {
// CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
-// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
+// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK14: omp.body.continue:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6197,7 +6197,7 @@ int main() {
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -6298,7 +6298,7 @@ int main() {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -6445,7 +6445,7 @@ int main() {
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -8015,7 +8015,7 @@ int main() {
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -8024,7 +8024,7 @@ int main() {
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -8091,7 +8091,7 @@ int main() {
// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -8100,7 +8100,7 @@ int main() {
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -8186,10 +8186,10 @@ int main() {
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
-// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
index 5c9b5be7444d7..e17961e76ae39 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
@@ -763,7 +763,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -822,7 +822,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -1264,7 +1264,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -1323,7 +1323,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -2087,7 +2087,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -2146,7 +2146,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -2588,7 +2588,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -2647,7 +2647,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -3411,7 +3411,7 @@ int main() {
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -3470,7 +3470,7 @@ int main() {
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then:
@@ -3912,7 +3912,7 @@ int main() {
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -3971,7 +3971,7 @@ int main() {
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then:
@@ -4735,7 +4735,7 @@ int main() {
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -4794,7 +4794,7 @@ int main() {
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then:
@@ -5236,7 +5236,7 @@ int main() {
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -5295,7 +5295,7 @@ int main() {
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then:
@@ -6059,7 +6059,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -6118,7 +6118,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -6560,7 +6560,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -6619,7 +6619,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -7383,7 +7383,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -7442,7 +7442,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -7884,7 +7884,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -7943,7 +7943,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -8707,7 +8707,7 @@ int main() {
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -8766,7 +8766,7 @@ int main() {
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then:
@@ -9208,7 +9208,7 @@ int main() {
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -9267,7 +9267,7 @@ int main() {
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then:
@@ -10031,7 +10031,7 @@ int main() {
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -10090,7 +10090,7 @@ int main() {
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then:
@@ -10532,7 +10532,7 @@ int main() {
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -10591,7 +10591,7 @@ int main() {
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then:
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
index 470a213961f6e..38d9f4673b0bb 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
@@ -213,11 +213,11 @@ int main() {
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -338,9 +338,9 @@ int main() {
// CHECK1-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8
// CHECK1-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK1-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK1-NEXT: store float [[TMP29]], float* [[CONV2]], align 8
+// CHECK1-NEXT: store float [[TMP29]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void
@@ -459,9 +459,9 @@ int main() {
// CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4
-// CHECK1-NEXT: store float [[TMP24]], float* [[CONV2]], align 8
+// CHECK1-NEXT: store float [[TMP24]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void
@@ -518,11 +518,11 @@ int main() {
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -643,9 +643,9 @@ int main() {
// CHECK2-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8
// CHECK2-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK2-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK2-NEXT: store float [[TMP29]], float* [[CONV2]], align 8
+// CHECK2-NEXT: store float [[TMP29]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void
@@ -764,9 +764,9 @@ int main() {
// CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK2-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4
-// CHECK2-NEXT: store float [[TMP24]], float* [[CONV2]], align 8
+// CHECK2-NEXT: store float [[TMP24]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void
@@ -1484,12 +1484,12 @@ int main() {
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -1610,7 +1610,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
@@ -1635,7 +1635,7 @@ int main() {
// CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK5-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8
+// CHECK5-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
@@ -1776,7 +1776,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4
-// CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
@@ -1801,7 +1801,7 @@ int main() {
// CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK5-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8
+// CHECK5-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
@@ -1992,7 +1992,7 @@ int main() {
// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2105,7 +2105,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK5-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false)
@@ -2265,7 +2265,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4
-// CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
@@ -2509,12 +2509,12 @@ int main() {
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -2635,7 +2635,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
@@ -2660,7 +2660,7 @@ int main() {
// CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK6-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8
+// CHECK6-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
@@ -2801,7 +2801,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4
-// CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
@@ -2826,7 +2826,7 @@ int main() {
// CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK6-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8
+// CHECK6-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
@@ -3017,7 +3017,7 @@ int main() {
// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -3130,7 +3130,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK6-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false)
@@ -3290,7 +3290,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4
-// CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
index 364dac905a3d2..86235945dd3b3 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
@@ -7797,7 +7797,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -7832,7 +7832,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -7878,7 +7878,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -7931,7 +7931,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8019,7 +8019,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -8054,7 +8054,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8100,7 +8100,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -8153,7 +8153,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8245,11 +8245,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8288,7 +8288,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8305,7 +8305,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -8336,11 +8336,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8419,7 +8419,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8507,7 +8507,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -8542,7 +8542,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8588,7 +8588,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -8641,7 +8641,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8729,11 +8729,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8772,7 +8772,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8818,11 +8818,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8878,7 +8878,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -8901,7 +8901,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -9413,7 +9413,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9473,7 +9473,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9526,7 +9526,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -9752,7 +9752,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9812,7 +9812,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9865,7 +9865,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -10316,7 +10316,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -10351,7 +10351,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10397,7 +10397,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -10450,7 +10450,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10538,7 +10538,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -10573,7 +10573,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10619,7 +10619,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -10672,7 +10672,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10764,11 +10764,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -10807,7 +10807,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10824,7 +10824,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -10855,11 +10855,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -10938,7 +10938,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -11026,7 +11026,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -11061,7 +11061,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -11107,7 +11107,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -11160,7 +11160,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -11248,11 +11248,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11291,7 +11291,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -11337,11 +11337,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11397,7 +11397,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -11420,7 +11420,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -11932,7 +11932,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11992,7 +11992,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -12045,7 +12045,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -12271,7 +12271,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -12331,7 +12331,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -12384,7 +12384,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -17669,7 +17669,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -17704,7 +17704,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -17750,7 +17750,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -17803,7 +17803,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -17891,7 +17891,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -17926,7 +17926,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -17972,7 +17972,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -18025,7 +18025,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -18117,11 +18117,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18160,7 +18160,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -18177,7 +18177,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -18208,11 +18208,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18291,7 +18291,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -18379,7 +18379,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -18414,7 +18414,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -18460,7 +18460,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -18513,7 +18513,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -18601,11 +18601,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18644,7 +18644,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -18690,11 +18690,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18750,7 +18750,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -18773,7 +18773,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -19285,7 +19285,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -19345,7 +19345,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -19398,7 +19398,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -19624,7 +19624,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -19684,7 +19684,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -19737,7 +19737,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -20188,7 +20188,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20223,7 +20223,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20269,7 +20269,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20322,7 +20322,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20410,7 +20410,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20445,7 +20445,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20491,7 +20491,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20544,7 +20544,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20636,11 +20636,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -20679,7 +20679,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20696,7 +20696,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -20727,11 +20727,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4
// CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -20810,7 +20810,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20898,7 +20898,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20933,7 +20933,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20979,7 +20979,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -21032,7 +21032,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -21120,11 +21120,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21163,7 +21163,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -21209,11 +21209,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4
// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21269,7 +21269,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -21292,7 +21292,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -21804,7 +21804,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21864,7 +21864,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21917,7 +21917,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -22143,7 +22143,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -22203,7 +22203,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -22256,7 +22256,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
index ab2d571b7d60f..bad61fd7a674e 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
@@ -261,14 +261,14 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -304,7 +304,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -356,7 +356,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -383,7 +383,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done:
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
@@ -424,7 +424,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -438,9 +438,9 @@ int target_teams_fun(int *g){
// CHECK1: omp.precond.then:
// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
@@ -512,7 +512,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
-// CHECK1-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done:
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
@@ -538,7 +538,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -573,7 +573,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -619,7 +619,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11
@@ -684,7 +684,7 @@ int target_teams_fun(int *g){
// CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -972,14 +972,14 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1015,7 +1015,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1067,7 +1067,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1094,7 +1094,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK2: .omp.final.done:
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
@@ -1135,7 +1135,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1149,9 +1149,9 @@ int target_teams_fun(int *g){
// CHECK2: omp.precond.then:
// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK2-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
@@ -1223,7 +1223,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
-// CHECK2-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK2: .omp.final.done:
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
@@ -1249,7 +1249,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -1284,7 +1284,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -1330,7 +1330,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11
@@ -1395,7 +1395,7 @@ int target_teams_fun(int *g){
// CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3475,14 +3475,14 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3518,7 +3518,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3570,7 +3570,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3597,7 +3597,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK9-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK9: .omp.final.done:
// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
@@ -3638,7 +3638,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3652,9 +3652,9 @@ int target_teams_fun(int *g){
// CHECK9: omp.precond.then:
// CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
@@ -3726,7 +3726,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK9-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
-// CHECK9-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK9: .omp.final.done:
// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
@@ -3752,7 +3752,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3787,7 +3787,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -3833,7 +3833,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12
@@ -3898,7 +3898,7 @@ int target_teams_fun(int *g){
// CHECK9-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -4009,14 +4009,14 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV5]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4052,7 +4052,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -4104,7 +4104,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[I_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[I_CASTED]], align 8
-// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4131,7 +4131,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[DIV11:%.*]] = sdiv i32 [[SUB10]], 1
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV11]], 1
// CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK10-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD12]], i32* [[CONV]], align 4
// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK10: .omp.final.done:
// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
@@ -4172,7 +4172,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -4186,9 +4186,9 @@ int target_teams_fun(int *g){
// CHECK10: omp.precond.then:
// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 0
// CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[ARRAYDECAY]], i64 8) ]
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTLINEAR_START]], align 4
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTLINEAR_STEP]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
@@ -4260,7 +4260,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
// CHECK10-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 1
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
-// CHECK10-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD15]], i32* [[CONV]], align 4
// CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK10: .omp.final.done:
// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
@@ -4286,7 +4286,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4321,7 +4321,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
@@ -4367,7 +4367,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12
+// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12
@@ -4432,7 +4432,7 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
index b7b088652fdf7..bdd4d313ede16 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
@@ -1461,11 +1461,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1511,9 +1511,9 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -1568,11 +1568,11 @@ int main (int argc, char **argv) {
// CHECK9: omp.inner.for.body:
// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
-// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5
-// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8, !llvm.access.group !5
+// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5
// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5
@@ -1653,9 +1653,9 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -2162,11 +2162,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -2212,9 +2212,9 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -2269,11 +2269,11 @@ int main (int argc, char **argv) {
// CHECK10: omp.inner.for.body:
// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5
-// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5
-// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8, !llvm.access.group !5
+// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5
// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5
@@ -2354,9 +2354,9 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
index 73d2762a6c129..1fe8bf844358d 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
@@ -3295,7 +3295,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3330,7 +3330,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3376,7 +3376,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9
@@ -3441,7 +3441,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3541,7 +3541,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3576,7 +3576,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3622,7 +3622,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18
+// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18
// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18
@@ -3687,7 +3687,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3791,11 +3791,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -3834,7 +3834,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3851,7 +3851,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -3882,11 +3882,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24
-// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !24
+// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
@@ -3977,7 +3977,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -4495,7 +4495,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -4528,7 +4528,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -4555,7 +4555,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
@@ -4949,7 +4949,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -4984,7 +4984,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -5030,7 +5030,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9
@@ -5095,7 +5095,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -5195,7 +5195,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -5230,7 +5230,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -5276,7 +5276,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18
+// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18
// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18
@@ -5341,7 +5341,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -5445,11 +5445,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -5488,7 +5488,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -5505,7 +5505,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -5536,11 +5536,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24
-// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !24
+// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
@@ -5631,7 +5631,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -6149,7 +6149,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -6182,7 +6182,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -6209,7 +6209,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
index f1f72eee7f86f..e900eb9a3323a 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
@@ -404,11 +404,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -507,11 +507,11 @@ int main() {
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
@@ -682,7 +682,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -694,9 +694,9 @@ int main() {
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -904,7 +904,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1005,7 +1005,7 @@ int main() {
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
@@ -1159,7 +1159,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1494,11 +1494,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1597,11 +1597,11 @@ int main() {
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
@@ -1772,7 +1772,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1784,9 +1784,9 @@ int main() {
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1994,7 +1994,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2095,7 +2095,7 @@ int main() {
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
@@ -2249,7 +2249,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -4638,7 +4638,7 @@ int main() {
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK5-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4647,7 +4647,7 @@ int main() {
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4714,7 +4714,7 @@ int main() {
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
@@ -4723,7 +4723,7 @@ int main() {
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
@@ -4816,10 +4816,10 @@ int main() {
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
-// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
+// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
-// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
+// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -5006,7 +5006,7 @@ int main() {
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK6-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -5015,7 +5015,7 @@ int main() {
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5082,7 +5082,7 @@ int main() {
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
@@ -5091,7 +5091,7 @@ int main() {
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
-// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
@@ -5184,10 +5184,10 @@ int main() {
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
-// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
+// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
-// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
+// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -6818,11 +6818,11 @@ int main() {
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -6921,11 +6921,11 @@ int main() {
// CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !6
+// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6
-// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !6
+// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6
@@ -7096,7 +7096,7 @@ int main() {
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
-// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !10
+// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -7108,9 +7108,9 @@ int main() {
// CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10
// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
-// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !10
+// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10
+// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK13: omp.body.continue:
// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7174,7 +7174,7 @@ int main() {
// CHECK13-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK13-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK13-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -7275,7 +7275,7 @@ int main() {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !15
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !15
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15
@@ -7429,7 +7429,7 @@ int main() {
// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18
+// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -7585,11 +7585,11 @@ int main() {
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -7688,11 +7688,11 @@ int main() {
// CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !6
+// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6
-// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !6
+// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6
@@ -7863,7 +7863,7 @@ int main() {
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
-// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !10
+// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -7875,9 +7875,9 @@ int main() {
// CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10
// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
-// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !10
+// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10
+// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !10
// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK14: omp.body.continue:
// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7941,7 +7941,7 @@ int main() {
// CHECK14-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK14-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK14-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -8042,7 +8042,7 @@ int main() {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !15
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !15
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15
@@ -8196,7 +8196,7 @@ int main() {
// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18
+// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -9829,7 +9829,7 @@ int main() {
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK17-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -9838,7 +9838,7 @@ int main() {
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -9905,7 +9905,7 @@ int main() {
// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !5
@@ -9914,7 +9914,7 @@ int main() {
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !5
-// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !5
+// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !5
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
@@ -10007,10 +10007,10 @@ int main() {
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
-// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9
// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9
-// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !9
+// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !9
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
index ca95218641026..a2844f97aa936 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
@@ -157,7 +157,7 @@ int main() {
// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -214,7 +214,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
@@ -298,7 +298,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
-// CHECK1-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK1-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -860,7 +860,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -919,7 +919,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !36
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !36
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -1403,7 +1403,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -1462,7 +1462,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -1631,7 +1631,7 @@ int main() {
// CHECK2-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -1688,7 +1688,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
@@ -1772,7 +1772,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
-// CHECK2-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK2-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2334,7 +2334,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -2393,7 +2393,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !36
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !36
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -2877,7 +2877,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -2936,7 +2936,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -3105,7 +3105,7 @@ int main() {
// CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -3162,7 +3162,7 @@ int main() {
// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9
+// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !9
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK3-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
@@ -3246,7 +3246,7 @@ int main() {
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
-// CHECK3-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14
+// CHECK3-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !14
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -3808,7 +3808,7 @@ int main() {
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -3859,7 +3859,7 @@ int main() {
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK3: omp_if.then:
@@ -3874,13 +3874,13 @@ int main() {
// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34
+// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
// CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
-// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34
+// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then5:
@@ -3915,13 +3915,13 @@ int main() {
// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK3-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK3: omp_if.then15:
@@ -3989,7 +3989,7 @@ int main() {
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -4117,7 +4117,7 @@ int main() {
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -4585,7 +4585,7 @@ int main() {
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -4644,7 +4644,7 @@ int main() {
// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54
+// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -4813,7 +4813,7 @@ int main() {
// CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -4870,7 +4870,7 @@ int main() {
// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9
+// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !9
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK4-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !9
@@ -4954,7 +4954,7 @@ int main() {
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
-// CHECK4-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14
+// CHECK4-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !10, !llvm.access.group !14
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -5516,7 +5516,7 @@ int main() {
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -5567,7 +5567,7 @@ int main() {
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK4: omp_if.then:
@@ -5582,13 +5582,13 @@ int main() {
// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34
+// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
-// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !34
+// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !34
// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then5:
@@ -5623,13 +5623,13 @@ int main() {
// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK4-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK4: omp_if.then15:
@@ -5697,7 +5697,7 @@ int main() {
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -5825,7 +5825,7 @@ int main() {
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -6293,7 +6293,7 @@ int main() {
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -6352,7 +6352,7 @@ int main() {
// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !54
+// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !54
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -7707,7 +7707,7 @@ int main() {
// CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -7764,7 +7764,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
@@ -7848,7 +7848,7 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK9-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK9-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK9: omp.body.continue:
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8410,7 +8410,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -8469,7 +8469,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !40
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !40
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -8953,7 +8953,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -9012,7 +9012,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -9181,7 +9181,7 @@ int main() {
// CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -9238,7 +9238,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
@@ -9322,7 +9322,7 @@ int main() {
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK10-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK10-NEXT: store i32 0, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK10: omp.body.continue:
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9884,7 +9884,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -9943,7 +9943,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !40
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !40
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -10427,7 +10427,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -10486,7 +10486,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -10655,7 +10655,7 @@ int main() {
// CHECK11-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -10712,7 +10712,7 @@ int main() {
// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !13
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
@@ -10796,7 +10796,7 @@ int main() {
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK11-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18
+// CHECK11-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !18
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -11358,7 +11358,7 @@ int main() {
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -11409,7 +11409,7 @@ int main() {
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK11: omp_if.then:
@@ -11424,13 +11424,13 @@ int main() {
// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38
+// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
-// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38
+// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then5:
@@ -11465,13 +11465,13 @@ int main() {
// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK11-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK11: omp_if.then15:
@@ -11539,7 +11539,7 @@ int main() {
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -11667,7 +11667,7 @@ int main() {
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -12135,7 +12135,7 @@ int main() {
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -12194,7 +12194,7 @@ int main() {
// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58
+// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -12363,7 +12363,7 @@ int main() {
// CHECK12-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[ARG_CASTED]], align 8
@@ -12420,7 +12420,7 @@ int main() {
// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13
+// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !13
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARG_CASTED]] to i32*
// CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[ARG_CASTED]], align 8, !llvm.access.group !13
@@ -12504,7 +12504,7 @@ int main() {
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK12-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18
+// CHECK12-NEXT: store i32 0, i32* [[CONV]], align 4, !nontemporal !14, !llvm.access.group !18
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK12: omp.body.continue:
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -13066,7 +13066,7 @@ int main() {
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -13117,7 +13117,7 @@ int main() {
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK12: omp_if.then:
@@ -13132,13 +13132,13 @@ int main() {
// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38
+// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
-// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38
+// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then5:
@@ -13173,13 +13173,13 @@ int main() {
// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK12-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK12: omp_if.then15:
@@ -13247,7 +13247,7 @@ int main() {
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -13375,7 +13375,7 @@ int main() {
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -13843,7 +13843,7 @@ int main() {
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -13902,7 +13902,7 @@ int main() {
// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !58
+// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !58
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
index 1887c26c0d8cd..03e4bae0c9bb2 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
@@ -213,11 +213,11 @@ int main() {
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -345,9 +345,9 @@ int main() {
// CHECK1-NEXT: [[TMP29:%.*]] = load double, double* [[TMP28]], align 8
// CHECK1-NEXT: store volatile double [[TMP29]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK1-NEXT: store float [[TMP31]], float* [[CONV2]], align 8
+// CHECK1-NEXT: store float [[TMP31]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void
@@ -473,9 +473,9 @@ int main() {
// CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 8
// CHECK1-NEXT: store volatile double [[TMP24]], double* [[TMP2]], align 8
// CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK1-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR11]], align 4
-// CHECK1-NEXT: store float [[TMP26]], float* [[CONV2]], align 8
+// CHECK1-NEXT: store float [[TMP26]], float* [[CONV2]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void
@@ -532,11 +532,11 @@ int main() {
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -664,9 +664,9 @@ int main() {
// CHECK2-NEXT: [[TMP29:%.*]] = load double, double* [[TMP28]], align 8
// CHECK2-NEXT: store volatile double [[TMP29]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[TMP30]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK2-NEXT: store float [[TMP31]], float* [[CONV2]], align 8
+// CHECK2-NEXT: store float [[TMP31]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void
@@ -792,9 +792,9 @@ int main() {
// CHECK2-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 8
// CHECK2-NEXT: store volatile double [[TMP24]], double* [[TMP2]], align 8
// CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK2-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[TMP25]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR11]], align 4
-// CHECK2-NEXT: store float [[TMP26]], float* [[CONV2]], align 8
+// CHECK2-NEXT: store float [[TMP26]], float* [[CONV2]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void
@@ -1540,12 +1540,12 @@ int main() {
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -1673,7 +1673,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK5-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP30:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 8, i1 false)
@@ -1698,7 +1698,7 @@ int main() {
// CHECK5-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP35]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK5-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 8
+// CHECK5-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
@@ -1846,7 +1846,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR5]], align 4
-// CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
@@ -1871,7 +1871,7 @@ int main() {
// CHECK5-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false)
// CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK5-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 8
+// CHECK5-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 4
// CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK5: .omp.lastprivate.done:
// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
@@ -2062,7 +2062,7 @@ int main() {
// CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2182,7 +2182,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
@@ -2349,7 +2349,7 @@ int main() {
// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK5: .omp.lastprivate.then:
// CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR4]], align 4
-// CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
@@ -2593,12 +2593,12 @@ int main() {
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -2726,7 +2726,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP27]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK6-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP30:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 8, i1 false)
@@ -2751,7 +2751,7 @@ int main() {
// CHECK6-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP35]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK6-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 8
+// CHECK6-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
@@ -2899,7 +2899,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR5]], align 4
-// CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
@@ -2924,7 +2924,7 @@ int main() {
// CHECK6-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[TMP34]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false)
// CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[SVAR10]], align 4
-// CHECK6-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 8
+// CHECK6-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 4
// CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK6: .omp.lastprivate.done:
// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
@@ -3115,7 +3115,7 @@ int main() {
// CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -3235,7 +3235,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
@@ -3402,7 +3402,7 @@ int main() {
// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK6: .omp.lastprivate.then:
// CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR4]], align 4
-// CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 [[TMP27]], i32* [[CONV]], align 4
// CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 8, i1 false)
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
index da7a6b1712ce6..c28b90653caa2 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
@@ -9127,7 +9127,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -9162,7 +9162,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -9208,7 +9208,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
@@ -9273,7 +9273,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -9373,7 +9373,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -9408,7 +9408,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -9454,7 +9454,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
@@ -9519,7 +9519,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -9623,11 +9623,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9666,7 +9666,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -9683,7 +9683,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -9714,11 +9714,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
-// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28
+// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -9809,7 +9809,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -9909,7 +9909,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -9944,7 +9944,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -9990,7 +9990,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
@@ -10055,7 +10055,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10155,11 +10155,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -10198,7 +10198,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10244,11 +10244,11 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
-// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40
+// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -10316,7 +10316,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -10339,7 +10339,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -10891,7 +10891,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -10951,7 +10951,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -11011,7 +11011,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -11258,7 +11258,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11318,7 +11318,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -11378,7 +11378,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -11836,7 +11836,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -11871,7 +11871,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -11917,7 +11917,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
@@ -11982,7 +11982,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12082,7 +12082,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -12117,7 +12117,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12163,7 +12163,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
@@ -12228,7 +12228,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12332,11 +12332,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -12375,7 +12375,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12392,7 +12392,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -12423,11 +12423,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
-// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28
+// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -12518,7 +12518,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12618,7 +12618,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -12653,7 +12653,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12699,7 +12699,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
@@ -12764,7 +12764,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12864,11 +12864,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -12907,7 +12907,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -12953,11 +12953,11 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
-// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40
+// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -13025,7 +13025,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -13048,7 +13048,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -13600,7 +13600,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -13660,7 +13660,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -13720,7 +13720,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -13967,7 +13967,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -14027,7 +14027,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -14087,7 +14087,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -19759,7 +19759,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -19794,7 +19794,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -19840,7 +19840,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
@@ -19905,7 +19905,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20005,7 +20005,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20040,7 +20040,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20086,7 +20086,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
@@ -20151,7 +20151,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20255,11 +20255,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -20298,7 +20298,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20315,7 +20315,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -20346,11 +20346,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
-// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28
+// CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK17-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -20441,7 +20441,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20541,7 +20541,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -20576,7 +20576,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20622,7 +20622,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
@@ -20687,7 +20687,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20787,11 +20787,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -20830,7 +20830,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20876,11 +20876,11 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
-// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40
+// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -20948,7 +20948,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -20971,7 +20971,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -21523,7 +21523,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21583,7 +21583,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -21643,7 +21643,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -21890,7 +21890,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21950,7 +21950,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -22010,7 +22010,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -22468,7 +22468,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -22503,7 +22503,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -22549,7 +22549,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !13
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !13
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !13
@@ -22614,7 +22614,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -22714,7 +22714,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -22749,7 +22749,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -22795,7 +22795,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !22
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !22
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !22
@@ -22860,7 +22860,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -22964,11 +22964,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -23007,7 +23007,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -23024,7 +23024,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -23055,11 +23055,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !28
-// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !28
+// CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !28
// CHECK18-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -23150,7 +23150,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -23250,7 +23250,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -23285,7 +23285,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -23331,7 +23331,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !34
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !34
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !34
@@ -23396,7 +23396,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -23496,11 +23496,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -23539,7 +23539,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -23585,11 +23585,11 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP19]], i32* [[CONV8]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !40
-// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !40
+// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV9]], align 4, !llvm.access.group !40
// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -23657,7 +23657,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -23680,7 +23680,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -24232,7 +24232,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -24292,7 +24292,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -24352,7 +24352,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -24599,7 +24599,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -24659,7 +24659,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -24719,7 +24719,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
index 04016eb544e0b..5aa6962c06de4 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
@@ -629,10 +629,10 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -824,7 +824,7 @@ int bar(int n){
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -899,7 +899,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK1-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK1: .omp.final.then:
-// CHECK1-NEXT: store i32 10, i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK1: .omp.final.done:
// CHECK1-NEXT: ret void
@@ -912,7 +912,7 @@ int bar(int n){
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -968,11 +968,11 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29
-// CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1006,11 +1006,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1069,14 +1069,14 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1130,7 +1130,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -1212,9 +1212,9 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK1-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK1-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -1625,7 +1625,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1693,7 +1693,7 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1751,19 +1751,19 @@ int bar(int n){
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -1804,9 +1804,9 @@ int bar(int n){
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -1859,19 +1859,19 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !41
-// CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !41
+// CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41
+// CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !41
-// CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !41
+// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41
+// CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !41
+// CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -1925,11 +1925,11 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -1991,14 +1991,14 @@ int bar(int n){
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
-// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
+// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -2368,10 +2368,10 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2563,7 +2563,7 @@ int bar(int n){
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2638,7 +2638,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK2-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK2: .omp.final.then:
-// CHECK2-NEXT: store i32 10, i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK2: .omp.final.done:
// CHECK2-NEXT: ret void
@@ -2651,7 +2651,7 @@ int bar(int n){
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2707,11 +2707,11 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29
-// CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !29
+// CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2745,11 +2745,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -2808,14 +2808,14 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
-// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
+// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
+// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -2869,7 +2869,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -2951,9 +2951,9 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK2-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK2-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK2-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -3364,7 +3364,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3432,7 +3432,7 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3490,19 +3490,19 @@ int bar(int n){
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK2-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -3543,9 +3543,9 @@ int bar(int n){
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -3598,19 +3598,19 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !41
-// CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !41
+// CHECK2-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41
+// CHECK2-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !41
-// CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !41
+// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41
+// CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK2-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK2-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK2-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !41
+// CHECK2-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -3664,11 +3664,11 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -3730,14 +3730,14 @@ int bar(int n){
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
-// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
+// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
+// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -4103,7 +4103,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4378,7 +4378,7 @@ int bar(int n){
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4434,11 +4434,11 @@ int bar(int n){
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -4474,7 +4474,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -4535,11 +4535,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -5208,11 +5208,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -5309,16 +5309,16 @@ int bar(int n){
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
-// CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
+// CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !42
-// CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !42
+// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42
+// CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !42
+// CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -5374,7 +5374,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -5438,11 +5438,11 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
-// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -5808,7 +5808,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6083,7 +6083,7 @@ int bar(int n){
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6139,11 +6139,11 @@ int bar(int n){
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !30
+// CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6179,7 +6179,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -6240,11 +6240,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
-// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
+// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK4: omp.body.continue:
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6913,11 +6913,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK4-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -7014,16 +7014,16 @@ int bar(int n){
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK4-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
-// CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
+// CHECK4-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !42
-// CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !42
+// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42
+// CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK4-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK4-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !42
+// CHECK4-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
// CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -7079,7 +7079,7 @@ int bar(int n){
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -7143,11 +7143,11 @@ int bar(int n){
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
-// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -7517,10 +7517,10 @@ int bar(int n){
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7712,7 +7712,7 @@ int bar(int n){
// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -7787,7 +7787,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK5-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK5: .omp.final.then:
-// CHECK5-NEXT: store i32 10, i32* [[CONV]], align 8
+// CHECK5-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK5: .omp.final.done:
// CHECK5-NEXT: ret void
@@ -7800,7 +7800,7 @@ int bar(int n){
// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7856,11 +7856,11 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !30
+// CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !30
+// CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -7894,11 +7894,11 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -7957,14 +7957,14 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33
-// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
+// CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -8018,7 +8018,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -8100,9 +8100,9 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !36
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK5-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !36
+// CHECK5-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -8539,11 +8539,11 @@ int bar(int n){
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -8605,7 +8605,7 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then:
@@ -8620,7 +8620,7 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !39
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39
// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK5-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -8656,7 +8656,7 @@ int bar(int n){
// CHECK5-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK5-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
-// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK5-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK5-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -8716,19 +8716,19 @@ int bar(int n){
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK5-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -8769,9 +8769,9 @@ int bar(int n){
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -8824,19 +8824,19 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK5-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44
-// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
+// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK5-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !44
-// CHECK5-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !44
+// CHECK5-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44
+// CHECK5-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44
// CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !44
-// CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !44
+// CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44
+// CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK5-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK5-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !44
+// CHECK5-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -8890,11 +8890,11 @@ int bar(int n){
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -8956,14 +8956,14 @@ int bar(int n){
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !47
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !47
-// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !47
+// CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47
+// CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !47
+// CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
// CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -9333,10 +9333,10 @@ int bar(int n){
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK6-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9528,7 +9528,7 @@ int bar(int n){
// CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -9603,7 +9603,7 @@ int bar(int n){
// CHECK6-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
// CHECK6-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK6: .omp.final.then:
-// CHECK6-NEXT: store i32 10, i32* [[CONV]], align 8
+// CHECK6-NEXT: store i32 10, i32* [[CONV]], align 4
// CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK6: .omp.final.done:
// CHECK6-NEXT: ret void
@@ -9616,7 +9616,7 @@ int bar(int n){
// CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9672,11 +9672,11 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !30
+// CHECK6-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK6-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !30
+// CHECK6-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9710,11 +9710,11 @@ int bar(int n){
// CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -9773,14 +9773,14 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
-// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33
+// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33
-// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
+// CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -9834,7 +9834,7 @@ int bar(int n){
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK6-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK6-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -9916,9 +9916,9 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
-// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !36
+// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK6-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !36
+// CHECK6-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK6-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -10355,11 +10355,11 @@ int bar(int n){
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -10421,7 +10421,7 @@ int bar(int n){
// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then:
@@ -10436,7 +10436,7 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
-// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !39
+// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39
// CHECK6-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK6-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -10472,7 +10472,7 @@ int bar(int n){
// CHECK6-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK6-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
-// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK6-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK6-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -10532,19 +10532,19 @@ int bar(int n){
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK6-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK6-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -10585,9 +10585,9 @@ int bar(int n){
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -10640,19 +10640,19 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK6-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44
-// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
+// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK6-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !44
-// CHECK6-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !44
+// CHECK6-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44
+// CHECK6-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44
// CHECK6-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK6-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK6-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !44
-// CHECK6-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !44
+// CHECK6-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44
+// CHECK6-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK6-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK6-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK6-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !44
+// CHECK6-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
// CHECK6-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -10706,11 +10706,11 @@ int bar(int n){
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK6-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK6-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK6-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK6-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -10772,14 +10772,14 @@ int bar(int n){
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47
-// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !47
+// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !47
-// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !47
+// CHECK6-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47
+// CHECK6-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK6-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK6-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !47
+// CHECK6-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
// CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -11145,7 +11145,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11420,7 +11420,7 @@ int bar(int n){
// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11476,11 +11476,11 @@ int bar(int n){
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
-// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !31
+// CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK7-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !31
+// CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -11516,7 +11516,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -11577,11 +11577,11 @@ int bar(int n){
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
-// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -12151,7 +12151,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -12212,7 +12212,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK7: omp_if.then:
@@ -12327,11 +12327,11 @@ int bar(int n){
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK7-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -12428,16 +12428,16 @@ int bar(int n){
// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK7-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
-// CHECK7-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK7-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !45
-// CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !45
+// CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45
+// CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK7-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK7-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK7-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !45
+// CHECK7-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -12493,7 +12493,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -12557,11 +12557,11 @@ int bar(int n){
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48
-// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !48
+// CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !48
+// CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -12927,7 +12927,7 @@ int bar(int n){
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK8-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -13202,7 +13202,7 @@ int bar(int n){
// CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -13258,11 +13258,11 @@ int bar(int n){
// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
-// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !31
+// CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK8-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK8-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !31
+// CHECK8-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -13298,7 +13298,7 @@ int bar(int n){
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -13359,11 +13359,11 @@ int bar(int n){
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
-// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK8: omp.body.continue:
// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -13933,7 +13933,7 @@ int bar(int n){
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK8-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK8-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -13994,7 +13994,7 @@ int bar(int n){
// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK8-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK8: omp_if.then:
@@ -14109,11 +14109,11 @@ int bar(int n){
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK8-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK8-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -14210,16 +14210,16 @@ int bar(int n){
// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK8-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
-// CHECK8-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
+// CHECK8-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
// CHECK8-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK8-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !45
-// CHECK8-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !45
+// CHECK8-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45
+// CHECK8-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK8-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK8-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK8-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK8-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !45
+// CHECK8-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
// CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -14275,7 +14275,7 @@ int bar(int n){
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK8-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK8-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK8-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -14339,11 +14339,11 @@ int bar(int n){
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48
// CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK8-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48
-// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !48
+// CHECK8-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK8-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !48
+// CHECK8-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
// CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -18655,10 +18655,10 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18743,7 +18743,7 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18799,11 +18799,11 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18837,11 +18837,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -18900,14 +18900,14 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21
-// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
+// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK17: omp.body.continue:
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -18961,7 +18961,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -19043,9 +19043,9 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
-// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK17-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK17-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -19123,19 +19123,19 @@ int bar(int n){
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -19176,9 +19176,9 @@ int bar(int n){
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -19231,19 +19231,19 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
-// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27
+// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27
-// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27
+// CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
+// CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27
-// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
+// CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -19302,7 +19302,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -19370,7 +19370,7 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -19420,11 +19420,11 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -19486,14 +19486,14 @@ int bar(int n){
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33
-// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
+// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -19534,10 +19534,10 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -19622,7 +19622,7 @@ int bar(int n){
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -19678,11 +19678,11 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK18-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19716,11 +19716,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -19779,14 +19779,14 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21
-// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
+// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK18: omp.body.continue:
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -19840,7 +19840,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -19922,9 +19922,9 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
-// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK18-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK18-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK18-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -20002,19 +20002,19 @@ int bar(int n){
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK18-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK18-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -20055,9 +20055,9 @@ int bar(int n){
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -20110,19 +20110,19 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK18-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
-// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27
+// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27
-// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27
+// CHECK18-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
+// CHECK18-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27
-// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
+// CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK18-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK18-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK18-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK18-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -20181,7 +20181,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
-// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -20249,7 +20249,7 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK18-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -20299,11 +20299,11 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -20365,14 +20365,14 @@ int bar(int n){
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
-// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !33
+// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !33
-// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
+// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !33
+// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -20414,7 +20414,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -20499,7 +20499,7 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -20555,11 +20555,11 @@ int bar(int n){
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
-// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -20595,7 +20595,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -20656,11 +20656,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
-// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK19: omp.body.continue:
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -20877,11 +20877,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -20978,16 +20978,16 @@ int bar(int n){
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
-// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28
+// CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28
-// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
+// CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -21163,7 +21163,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -21227,11 +21227,11 @@ int bar(int n){
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
-// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -21273,7 +21273,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -21358,7 +21358,7 @@ int bar(int n){
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -21414,11 +21414,11 @@ int bar(int n){
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
-// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK20-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -21454,7 +21454,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -21515,11 +21515,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
-// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK20: omp.body.continue:
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -21736,11 +21736,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK20-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -21837,16 +21837,16 @@ int bar(int n){
// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK20-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
-// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28
+// CHECK20-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28
-// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
+// CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK20-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK20-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK20-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK20-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK20-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -22022,7 +22022,7 @@ int bar(int n){
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -22086,11 +22086,11 @@ int bar(int n){
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
-// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !34
+// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -22131,10 +22131,10 @@ int bar(int n){
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK21-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -22219,7 +22219,7 @@ int bar(int n){
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -22275,11 +22275,11 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK21-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK21-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK21-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK21-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK21-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -22313,11 +22313,11 @@ int bar(int n){
// CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -22376,14 +22376,14 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
-// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
+// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21
-// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
+// CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue:
// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -22437,7 +22437,7 @@ int bar(int n){
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -22519,9 +22519,9 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
-// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK21-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK21-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -22599,19 +22599,19 @@ int bar(int n){
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK21-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK21-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK21-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -22652,9 +22652,9 @@ int bar(int n){
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK21-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -22707,19 +22707,19 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK21-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
-// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27
+// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK21-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27
-// CHECK21-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27
+// CHECK21-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
+// CHECK21-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27
-// CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
+// CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK21-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK21-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK21-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK21-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -22782,11 +22782,11 @@ int bar(int n){
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -22848,7 +22848,7 @@ int bar(int n){
// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then:
@@ -22863,7 +22863,7 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30
+// CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK21-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -22899,7 +22899,7 @@ int bar(int n){
// CHECK21-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK21-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
-// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK21-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK21-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -22951,11 +22951,11 @@ int bar(int n){
// CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -23017,14 +23017,14 @@ int bar(int n){
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
-// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !35
-// CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !35
+// CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35
+// CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !35
+// CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -23065,10 +23065,10 @@ int bar(int n){
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
-// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
+// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
+// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
// CHECK22-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -23153,7 +23153,7 @@ int bar(int n){
// CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -23209,11 +23209,11 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
-// CHECK22-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK22-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK22-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK22-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK22-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 8, !llvm.access.group !18
+// CHECK22-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -23247,11 +23247,11 @@ int bar(int n){
// CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
-// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -23310,14 +23310,14 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
-// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
+// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !21
-// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
+// CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !21
+// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK22: omp.body.continue:
// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -23371,7 +23371,7 @@ int bar(int n){
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
// CHECK22-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
// CHECK22-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
-// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
@@ -23453,9 +23453,9 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
-// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK22-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK22-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
// CHECK22-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double
@@ -23533,19 +23533,19 @@ int bar(int n){
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK22-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK22-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK22-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2
// CHECK22-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
-// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK22-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
// CHECK22-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1
// CHECK22-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
@@ -23586,9 +23586,9 @@ int bar(int n){
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK22-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
@@ -23641,19 +23641,19 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
// CHECK22-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
-// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !27
+// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK22-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 8, !llvm.access.group !27
-// CHECK22-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8, !llvm.access.group !27
+// CHECK22-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
+// CHECK22-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
// CHECK22-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
// CHECK22-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
-// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 8, !llvm.access.group !27
-// CHECK22-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK22-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
+// CHECK22-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK22-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
// CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
// CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
-// CHECK22-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 8, !llvm.access.group !27
+// CHECK22-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
// CHECK22-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
@@ -23716,11 +23716,11 @@ int bar(int n){
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK22-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
-// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4
// CHECK22-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
-// CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK22-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK22-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -23782,7 +23782,7 @@ int bar(int n){
// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
+// CHECK22-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then:
@@ -23797,7 +23797,7 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
-// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !30
+// CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
// CHECK22-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK22-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
// CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -23833,7 +23833,7 @@ int bar(int n){
// CHECK22-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
// CHECK22-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
// CHECK22-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
-// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
// CHECK22-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
// CHECK22-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -23885,11 +23885,11 @@ int bar(int n){
// CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
// CHECK22-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
-// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK22-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK22-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
// CHECK22-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK22-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK22-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
// CHECK22-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK22-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
@@ -23951,14 +23951,14 @@ int bar(int n){
// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
-// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
+// CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !35
-// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !35
+// CHECK22-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35
+// CHECK22-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK22-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
// CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
// CHECK22-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !35
+// CHECK22-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35
// CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
// CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
// CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
@@ -24000,7 +24000,7 @@ int bar(int n){
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK23-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -24085,7 +24085,7 @@ int bar(int n){
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -24141,11 +24141,11 @@ int bar(int n){
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
-// CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK23-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK23-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK23-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -24181,7 +24181,7 @@ int bar(int n){
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -24242,11 +24242,11 @@ int bar(int n){
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
-// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -24463,11 +24463,11 @@ int bar(int n){
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK23-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK23-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -24564,16 +24564,16 @@ int bar(int n){
// CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK23-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
-// CHECK23-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28
+// CHECK23-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28
-// CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
+// CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK23-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK23-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK23-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK23-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK23-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -24638,7 +24638,7 @@ int bar(int n){
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -24699,7 +24699,7 @@ int bar(int n){
// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then:
@@ -24804,7 +24804,7 @@ int bar(int n){
// CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -24868,11 +24868,11 @@ int bar(int n){
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
-// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !36
+// CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !36
+// CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
@@ -24914,7 +24914,7 @@ int bar(int n){
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
// CHECK24-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
-// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -24999,7 +24999,7 @@ int bar(int n){
// CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
// CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
-// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -25055,11 +25055,11 @@ int bar(int n){
// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
-// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK24-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
// CHECK24-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK24-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4, !llvm.access.group !19
+// CHECK24-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -25095,7 +25095,7 @@ int bar(int n){
// CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -25156,11 +25156,11 @@ int bar(int n){
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
-// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !22
+// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK24: omp.body.continue:
// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -25377,11 +25377,11 @@ int bar(int n){
// CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
-// CHECK24-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
-// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
+// CHECK24-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
// CHECK24-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
@@ -25478,16 +25478,16 @@ int bar(int n){
// CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK24-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
-// CHECK24-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !28
+// CHECK24-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
// CHECK24-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
// CHECK24-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
// CHECK24-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
-// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !28
-// CHECK24-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK24-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
+// CHECK24-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK24-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
// CHECK24-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
// CHECK24-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
-// CHECK24-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 4, !llvm.access.group !28
+// CHECK24-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
// CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
@@ -25552,7 +25552,7 @@ int bar(int n){
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
-// CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK24-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK24-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
@@ -25613,7 +25613,7 @@ int bar(int n){
// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
-// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then:
@@ -25718,7 +25718,7 @@ int bar(int n){
// CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK24-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
// CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
// CHECK24-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
// CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
@@ -25782,11 +25782,11 @@ int bar(int n){
// CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
// CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK24-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
-// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !36
+// CHECK24-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK24-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !36
+// CHECK24-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36
// CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
// CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
// CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
index 89a4e1d65a4f2..6e3c19d4421f7 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
@@ -1132,11 +1132,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1180,9 +1180,9 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
@@ -1602,11 +1602,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8
@@ -1650,9 +1650,9 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp
index 1a8ace57e5589..fb0cb638f50ce 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp
@@ -2333,7 +2333,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2367,7 +2367,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2461,7 +2461,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -2495,7 +2495,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2593,11 +2593,11 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -2634,7 +2634,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -2651,7 +2651,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
@@ -3335,7 +3335,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3369,7 +3369,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3463,7 +3463,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
@@ -3497,7 +3497,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3595,11 +3595,11 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -3636,7 +3636,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
@@ -3653,7 +3653,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP6]])
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp
index ce209edf36ac2..138ff30b199ac 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp
@@ -345,11 +345,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -446,7 +446,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -458,9 +458,9 @@ int main() {
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -701,7 +701,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -801,7 +801,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1149,11 +1149,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1250,7 +1250,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1262,9 +1262,9 @@ int main() {
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1505,7 +1505,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1605,7 +1605,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -4759,7 +4759,7 @@ int main() {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4768,7 +4768,7 @@ int main() {
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4833,10 +4833,10 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
-// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
-// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -5023,7 +5023,7 @@ int main() {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -5032,7 +5032,7 @@ int main() {
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5097,10 +5097,10 @@ int main() {
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
-// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
-// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp
index db176f5468882..f62acbff4b39f 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp
@@ -182,11 +182,11 @@ int main() {
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK1-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK1-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -305,9 +305,9 @@ int main() {
// CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP0]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK1-NEXT: store float [[TMP24]], float* [[CONV3]], align 8
+// CHECK1-NEXT: store float [[TMP24]], float* [[CONV3]], align 4
// CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK1: .omp.lastprivate.done:
// CHECK1-NEXT: ret void
@@ -368,11 +368,11 @@ int main() {
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[G1_CASTED]] to double*
// CHECK2-NEXT: store double [[TMP3]], double* [[CONV5]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV6]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load float, float* [[CONV3]], align 4
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
// CHECK2-NEXT: store float [[TMP7]], float* [[CONV7]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
@@ -491,9 +491,9 @@ int main() {
// CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
// CHECK2-NEXT: store volatile double [[TMP22]], double* [[TMP0]], align 8
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 8
+// CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR9]], align 4
-// CHECK2-NEXT: store float [[TMP24]], float* [[CONV3]], align 8
+// CHECK2-NEXT: store float [[TMP24]], float* [[CONV3]], align 4
// CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK2: .omp.lastprivate.done:
// CHECK2-NEXT: ret void
@@ -1077,12 +1077,12 @@ int main() {
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -1211,7 +1211,7 @@ int main() {
// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
@@ -1236,7 +1236,7 @@ int main() {
// CHECK9-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK9-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK9: .omp.lastprivate.done:
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]]
@@ -1427,7 +1427,7 @@ int main() {
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1553,7 +1553,7 @@ int main() {
// CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK9: .omp.lastprivate.then:
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK9-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
@@ -1797,12 +1797,12 @@ int main() {
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
// CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
// CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
@@ -1931,7 +1931,7 @@ int main() {
// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4
-// CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
@@ -1956,7 +1956,7 @@ int main() {
// CHECK10-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
// CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR8]], align 4
-// CHECK10-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 4
// CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK10: .omp.lastprivate.done:
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]]
@@ -2147,7 +2147,7 @@ int main() {
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2273,7 +2273,7 @@ int main() {
// CHECK10-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK10: .omp.lastprivate.then:
// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
-// CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
// CHECK10-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
diff --git a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp
index 007685e1d25bc..2508c7468749a 100644
--- a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp
@@ -450,9 +450,9 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -473,7 +473,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -515,7 +515,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void
@@ -538,7 +538,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void
@@ -588,14 +588,14 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -616,11 +616,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -907,9 +907,9 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -930,7 +930,7 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -972,7 +972,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void
@@ -995,7 +995,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void
@@ -1045,14 +1045,14 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1073,11 +1073,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void
//
//
@@ -1490,13 +1490,13 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -1516,7 +1516,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -1933,13 +1933,13 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -1959,7 +1959,7 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -1981,7 +1981,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void
@@ -2004,7 +2004,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void
@@ -2034,9 +2034,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2057,7 +2057,7 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2126,14 +2126,14 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2154,11 +2154,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void
//
//
@@ -2169,7 +2169,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void
@@ -2192,7 +2192,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void
@@ -2222,9 +2222,9 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2245,7 +2245,7 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2314,14 +2314,14 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2342,11 +2342,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void
//
//
@@ -2495,13 +2495,13 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2521,7 +2521,7 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2674,13 +2674,13 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2700,7 +2700,7 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2984,9 +2984,9 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3007,7 +3007,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3049,7 +3049,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void
@@ -3072,7 +3072,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void
@@ -3122,14 +3122,14 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3150,11 +3150,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void
//
//
@@ -3441,9 +3441,9 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3464,7 +3464,7 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3506,7 +3506,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void
@@ -3529,7 +3529,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void
@@ -3579,14 +3579,14 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3607,11 +3607,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void
//
//
@@ -4024,13 +4024,13 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -4050,7 +4050,7 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -4467,13 +4467,13 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -4493,7 +4493,7 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -4515,7 +4515,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void
@@ -4538,7 +4538,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void
@@ -4568,9 +4568,9 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4591,7 +4591,7 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -4660,14 +4660,14 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4688,11 +4688,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void
//
//
@@ -4703,7 +4703,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void
@@ -4726,7 +4726,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void
@@ -4756,9 +4756,9 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4779,7 +4779,7 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -4848,14 +4848,14 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4876,11 +4876,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void
//
//
@@ -5029,13 +5029,13 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -5055,7 +5055,7 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -5208,13 +5208,13 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0)
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -5234,7 +5234,7 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
diff --git a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
index d80366e55beb3..860b6ee596dc8 100644
--- a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
@@ -468,9 +468,9 @@ int bar(int n){
// CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -491,7 +491,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -536,8 +536,8 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void
@@ -560,7 +560,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK1-NEXT: ret void
@@ -610,14 +610,14 @@ int bar(int n){
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -638,11 +638,11 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -947,9 +947,9 @@ int bar(int n){
// CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -970,7 +970,7 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -1015,8 +1015,8 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void
@@ -1039,7 +1039,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK2-NEXT: ret void
@@ -1089,14 +1089,14 @@ int bar(int n){
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -1117,11 +1117,11 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK2-NEXT: ret void
//
//
@@ -1554,13 +1554,13 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -1580,7 +1580,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2017,13 +2017,13 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2043,7 +2043,7 @@ int bar(int n){
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2068,8 +2068,8 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void
@@ -2092,7 +2092,7 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK9-NEXT: ret void
@@ -2122,9 +2122,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2145,7 +2145,7 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2214,14 +2214,14 @@ int bar(int n){
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2242,11 +2242,11 @@ int bar(int n){
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK9-NEXT: ret void
//
//
@@ -2260,8 +2260,8 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void
@@ -2284,7 +2284,7 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK10-NEXT: ret void
@@ -2314,9 +2314,9 @@ int bar(int n){
// CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2337,7 +2337,7 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -2406,14 +2406,14 @@ int bar(int n){
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -2434,11 +2434,11 @@ int bar(int n){
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK10-NEXT: ret void
//
//
@@ -2590,13 +2590,13 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2616,7 +2616,7 @@ int bar(int n){
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -2772,13 +2772,13 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -2798,7 +2798,7 @@ int bar(int n){
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -3100,9 +3100,9 @@ int bar(int n){
// CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3123,7 +3123,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3168,8 +3168,8 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void
@@ -3192,7 +3192,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK17-NEXT: ret void
@@ -3242,14 +3242,14 @@ int bar(int n){
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3270,11 +3270,11 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK17-NEXT: ret void
//
//
@@ -3579,9 +3579,9 @@ int bar(int n){
// CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3602,7 +3602,7 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -3647,8 +3647,8 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void
@@ -3671,7 +3671,7 @@ int bar(int n){
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
// CHECK18-NEXT: ret void
@@ -3721,14 +3721,14 @@ int bar(int n){
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -3749,11 +3749,11 @@ int bar(int n){
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK18-NEXT: ret void
//
//
@@ -4186,13 +4186,13 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -4212,7 +4212,7 @@ int bar(int n){
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -4649,13 +4649,13 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -4675,7 +4675,7 @@ int bar(int n){
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -4700,8 +4700,8 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void
@@ -4724,7 +4724,7 @@ int bar(int n){
// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK25-NEXT: ret void
@@ -4754,9 +4754,9 @@ int bar(int n){
// CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4777,7 +4777,7 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -4846,14 +4846,14 @@ int bar(int n){
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4874,11 +4874,11 @@ int bar(int n){
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK25-NEXT: ret void
//
//
@@ -4892,8 +4892,8 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void
@@ -4916,7 +4916,7 @@ int bar(int n){
// CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
// CHECK26-NEXT: ret void
@@ -4946,9 +4946,9 @@ int bar(int n){
// CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP2]])
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -4969,7 +4969,7 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
@@ -5038,14 +5038,14 @@ int bar(int n){
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 2
// CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
// CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
-// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16*
// CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
@@ -5066,11 +5066,11 @@ int bar(int n){
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
-// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
-// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
-// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8
+// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
// CHECK26-NEXT: ret void
//
//
@@ -5222,13 +5222,13 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -5248,7 +5248,7 @@ int bar(int n){
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
@@ -5404,13 +5404,13 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16*
-// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4
+// CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2
// CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32
// CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 1024)
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
-// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16*
// CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
@@ -5430,7 +5430,7 @@ int bar(int n){
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
-// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
+// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
// CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
diff --git a/clang/test/OpenMP/teams_codegen.cpp b/clang/test/OpenMP/teams_codegen.cpp
index efbb8d648c6c5..40a815b8d352a 100644
--- a/clang/test/OpenMP/teams_codegen.cpp
+++ b/clang/test/OpenMP/teams_codegen.cpp
@@ -638,7 +638,7 @@ void foo() {
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK1-NEXT: ret void
@@ -670,7 +670,7 @@ void foo() {
// CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK1-NEXT: ret void
@@ -710,11 +710,11 @@ void foo() {
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 4
// CHECK1-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]]
// CHECK1-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32
@@ -1130,7 +1130,7 @@ void foo() {
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK2-NEXT: ret void
@@ -1162,7 +1162,7 @@ void foo() {
// CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32*
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]])
// CHECK2-NEXT: ret void
@@ -1202,11 +1202,11 @@ void foo() {
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 4
// CHECK2-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]]
// CHECK2-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32
@@ -3849,8 +3849,8 @@ void foo() {
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK33-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
-// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]])
// CHECK33-NEXT: ret void
@@ -3882,8 +3882,8 @@ void foo() {
// CHECK33-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
// CHECK33-NEXT: ret void
@@ -3916,8 +3916,8 @@ void foo() {
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
// CHECK34-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
-// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]])
// CHECK34-NEXT: ret void
@@ -3949,8 +3949,8 @@ void foo() {
// CHECK34-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32*
-// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]])
// CHECK34-NEXT: ret void
diff --git a/clang/test/OpenMP/teams_distribute_codegen.cpp b/clang/test/OpenMP/teams_distribute_codegen.cpp
index 6124911226a9d..24a4329d096b0 100644
--- a/clang/test/OpenMP/teams_distribute_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_codegen.cpp
@@ -328,8 +328,8 @@ int main (int argc, char **argv) {
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void
@@ -692,8 +692,8 @@ int main (int argc, char **argv) {
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void
@@ -3202,8 +3202,8 @@ int main (int argc, char **argv) {
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK25-NEXT: ret void
@@ -3562,8 +3562,8 @@ int main (int argc, char **argv) {
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK26-NEXT: ret void
diff --git a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp
index a16577e47b566..4737bdf9885db 100644
--- a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp
@@ -1969,7 +1969,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -2025,7 +2025,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -2881,7 +2881,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -2937,7 +2937,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
diff --git a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
index f766b6257c24a..d428cf999b1ea 100644
--- a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
@@ -348,11 +348,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -449,7 +449,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -461,9 +461,9 @@ int main() {
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -699,7 +699,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -799,7 +799,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1140,11 +1140,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1241,7 +1241,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1253,9 +1253,9 @@ int main() {
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1491,7 +1491,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1591,7 +1591,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -3418,7 +3418,7 @@ int main() {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -3427,7 +3427,7 @@ int main() {
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -3492,10 +3492,10 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
-// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -3675,7 +3675,7 @@ int main() {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -3684,7 +3684,7 @@ int main() {
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -3749,10 +3749,10 @@ int main() {
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
-// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
index c31965a4c6457..61d18a0eb0874 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
@@ -327,8 +327,8 @@ int main (int argc, char **argv) {
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void
@@ -901,8 +901,8 @@ int main (int argc, char **argv) {
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void
@@ -4806,8 +4806,8 @@ int main (int argc, char **argv) {
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK25-NEXT: ret void
@@ -5339,8 +5339,8 @@ int main (int argc, char **argv) {
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK26-NEXT: ret void
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
index 965e00ee1d5bc..2be4e769c21d7 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
@@ -3067,7 +3067,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -3124,7 +3124,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -3155,7 +3155,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -3710,7 +3710,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -3745,7 +3745,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -3772,7 +3772,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -4577,7 +4577,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -4634,7 +4634,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -4665,7 +4665,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -5220,7 +5220,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -5255,7 +5255,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -5282,7 +5282,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
index 22ba0d8197a06..bf2459ced3e82 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
@@ -382,11 +382,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -485,11 +485,11 @@ int main() {
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -653,7 +653,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -665,9 +665,9 @@ int main() {
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
+// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -870,7 +870,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -971,7 +971,7 @@ int main() {
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1118,7 +1118,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1446,11 +1446,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1549,11 +1549,11 @@ int main() {
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1717,7 +1717,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1729,9 +1729,9 @@ int main() {
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
+// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1934,7 +1934,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2035,7 +2035,7 @@ int main() {
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2182,7 +2182,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -4512,7 +4512,7 @@ int main() {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4521,7 +4521,7 @@ int main() {
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4588,7 +4588,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4597,7 +4597,7 @@ int main() {
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4683,10 +4683,10 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
-// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -4866,7 +4866,7 @@ int main() {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4875,7 +4875,7 @@ int main() {
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4942,7 +4942,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4951,7 +4951,7 @@ int main() {
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
+// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5037,10 +5037,10 @@ int main() {
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
-// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8
+// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
-// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8
+// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
index 77700887dab51..a52665e07e52e 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
@@ -769,7 +769,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -832,7 +832,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -1281,7 +1281,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -1344,7 +1344,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -2106,7 +2106,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -2169,7 +2169,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -2618,7 +2618,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -2681,7 +2681,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -3443,7 +3443,7 @@ int main() {
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -3506,7 +3506,7 @@ int main() {
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then:
@@ -3955,7 +3955,7 @@ int main() {
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -4018,7 +4018,7 @@ int main() {
// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK5: omp_if.then:
@@ -4780,7 +4780,7 @@ int main() {
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -4843,7 +4843,7 @@ int main() {
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then:
@@ -5292,7 +5292,7 @@ int main() {
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK6-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK6-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -5355,7 +5355,7 @@ int main() {
// CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK6: omp_if.then:
@@ -6117,7 +6117,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -6180,7 +6180,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -6629,7 +6629,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -6692,7 +6692,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -7454,7 +7454,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -7517,7 +7517,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -7966,7 +7966,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -8029,7 +8029,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -8791,7 +8791,7 @@ int main() {
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -8854,7 +8854,7 @@ int main() {
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then:
@@ -9303,7 +9303,7 @@ int main() {
// CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -9366,7 +9366,7 @@ int main() {
// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK13: omp_if.then:
@@ -10128,7 +10128,7 @@ int main() {
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -10191,7 +10191,7 @@ int main() {
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then:
@@ -10640,7 +10640,7 @@ int main() {
// CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK14-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK14-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -10703,7 +10703,7 @@ int main() {
// CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK14-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK14: omp_if.then:
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
index 7e35b20b4bf96..0e06a7cfa1163 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
@@ -346,7 +346,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -400,7 +400,7 @@ int main() {
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
@@ -1117,7 +1117,7 @@ int main() {
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
@@ -1498,7 +1498,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -1552,7 +1552,7 @@ int main() {
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
@@ -2269,7 +2269,7 @@ int main() {
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
@@ -2650,7 +2650,7 @@ int main() {
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -2704,7 +2704,7 @@ int main() {
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
@@ -3412,7 +3412,7 @@ int main() {
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
@@ -3802,7 +3802,7 @@ int main() {
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -3856,7 +3856,7 @@ int main() {
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
@@ -4564,7 +4564,7 @@ int main() {
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]])
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
index b1a46f0dfbb58..0ea08bb4d4124 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
@@ -8233,7 +8233,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -8290,7 +8290,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -8321,7 +8321,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8700,7 +8700,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -8786,7 +8786,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -8865,7 +8865,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -9372,7 +9372,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -9434,7 +9434,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9487,7 +9487,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -9714,7 +9714,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -9776,7 +9776,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -9829,7 +9829,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -10702,7 +10702,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -10759,7 +10759,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -10790,7 +10790,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11169,7 +11169,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -11255,7 +11255,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11334,7 +11334,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -11841,7 +11841,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -11903,7 +11903,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -11956,7 +11956,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -12183,7 +12183,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -12245,7 +12245,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -12298,7 +12298,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -17945,7 +17945,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -18002,7 +18002,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -18033,7 +18033,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18412,7 +18412,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -18498,7 +18498,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK17-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -18577,7 +18577,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -19084,7 +19084,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -19146,7 +19146,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -19199,7 +19199,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -19426,7 +19426,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -19488,7 +19488,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK17-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK17-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -19541,7 +19541,7 @@ int main (int argc, char **argv) {
// CHECK17-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -20414,7 +20414,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -20471,7 +20471,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -20502,7 +20502,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -20881,7 +20881,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -20967,7 +20967,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4
// CHECK18-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21046,7 +21046,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -21553,7 +21553,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -21615,7 +21615,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -21668,7 +21668,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -21895,7 +21895,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -21957,7 +21957,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK18-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK18-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4
// CHECK18-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
@@ -22010,7 +22010,7 @@ int main (int argc, char **argv) {
// CHECK18-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK18-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
index b3d27129b22df..4fa27a341fc52 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
@@ -347,8 +347,8 @@ int main (int argc, char **argv) {
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void
@@ -994,8 +994,8 @@ int main (int argc, char **argv) {
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void
@@ -6742,8 +6742,8 @@ int main (int argc, char **argv) {
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK25-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK25-NEXT: ret void
@@ -7353,8 +7353,8 @@ int main (int argc, char **argv) {
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK26-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB4]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK26-NEXT: ret void
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
index 0080196f4da05..16d84deb0e2ed 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
@@ -3780,7 +3780,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -3837,7 +3837,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -3868,7 +3868,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24
// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
@@ -4475,7 +4475,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -4510,7 +4510,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -4537,7 +4537,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
@@ -5404,7 +5404,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -5461,7 +5461,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -5492,7 +5492,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24
+// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24
// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24
@@ -6099,7 +6099,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -6134,7 +6134,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP1]])
@@ -6161,7 +6161,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
index 6eb15b78e96fb..b0a0e22909a80 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
@@ -385,11 +385,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -488,11 +488,11 @@ int main() {
// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
@@ -663,7 +663,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -675,9 +675,9 @@ int main() {
// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -887,7 +887,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -988,7 +988,7 @@ int main() {
// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
@@ -1142,7 +1142,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1477,11 +1477,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1580,11 +1580,11 @@ int main() {
// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5
@@ -1755,7 +1755,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -1767,9 +1767,9 @@ int main() {
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
-// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9
+// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 4, !llvm.access.group !9
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1979,7 +1979,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -2080,7 +2080,7 @@ int main() {
// CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14
// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14
@@ -2234,7 +2234,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
@@ -5935,7 +5935,7 @@ int main() {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -5944,7 +5944,7 @@ int main() {
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -6011,7 +6011,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
@@ -6020,7 +6020,7 @@ int main() {
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
-// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
@@ -6113,10 +6113,10 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
-// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
+// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
-// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
+// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -6303,7 +6303,7 @@ int main() {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -6312,7 +6312,7 @@ int main() {
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -6379,7 +6379,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4
@@ -6388,7 +6388,7 @@ int main() {
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4
-// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4
@@ -6481,10 +6481,10 @@ int main() {
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
-// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8
+// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !8
// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8
-// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8
+// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !8
// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
index 083654213f5e1..45182c7120324 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
@@ -822,7 +822,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -885,7 +885,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -1376,7 +1376,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -1439,7 +1439,7 @@ int main() {
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !56
+// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !56
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK1: omp_if.then:
@@ -2271,7 +2271,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -2334,7 +2334,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !38
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -2825,7 +2825,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -2888,7 +2888,7 @@ int main() {
// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56
// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !56
+// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !56
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK2: omp_if.then:
@@ -3720,7 +3720,7 @@ int main() {
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -3775,7 +3775,7 @@ int main() {
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK3: omp_if.then:
@@ -3790,13 +3790,13 @@ int main() {
// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35
+// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35
// CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35
-// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35
+// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then5:
@@ -3831,13 +3831,13 @@ int main() {
// CHECK3-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK3-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK3-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK3: omp_if.then15:
@@ -3905,7 +3905,7 @@ int main() {
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -4033,7 +4033,7 @@ int main() {
// CHECK3-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -4508,7 +4508,7 @@ int main() {
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -4571,7 +4571,7 @@ int main() {
// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !55
+// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !55
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK3: omp_if.then:
@@ -5403,7 +5403,7 @@ int main() {
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -5458,7 +5458,7 @@ int main() {
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK4: omp_if.then:
@@ -5473,13 +5473,13 @@ int main() {
// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35
// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35
+// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35
// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35
-// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35
+// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !35
// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then5:
@@ -5514,13 +5514,13 @@ int main() {
// CHECK4-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK4-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK4-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK4-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK4: omp_if.then15:
@@ -5588,7 +5588,7 @@ int main() {
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -5716,7 +5716,7 @@ int main() {
// CHECK4-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -6191,7 +6191,7 @@ int main() {
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -6254,7 +6254,7 @@ int main() {
// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55
// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !55
+// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !55
// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK4: omp_if.then:
@@ -8268,7 +8268,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -8331,7 +8331,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -8822,7 +8822,7 @@ int main() {
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK9-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK9-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -8885,7 +8885,7 @@ int main() {
// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !60
+// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !60
// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
@@ -9717,7 +9717,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -9780,7 +9780,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -10271,7 +10271,7 @@ int main() {
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK10-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK10-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -10334,7 +10334,7 @@ int main() {
// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60
// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !60
+// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !60
// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK10: omp_if.then:
@@ -11166,7 +11166,7 @@ int main() {
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -11221,7 +11221,7 @@ int main() {
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK11: omp_if.then:
@@ -11236,13 +11236,13 @@ int main() {
// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39
+// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39
// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39
-// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39
+// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then5:
@@ -11277,13 +11277,13 @@ int main() {
// CHECK11-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK11-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK11-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK11-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK11: omp_if.then15:
@@ -11351,7 +11351,7 @@ int main() {
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -11479,7 +11479,7 @@ int main() {
// CHECK11-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -11954,7 +11954,7 @@ int main() {
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -12017,7 +12017,7 @@ int main() {
// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !59
+// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !59
// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
@@ -12849,7 +12849,7 @@ int main() {
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -12904,7 +12904,7 @@ int main() {
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE6:%.*]]
// CHECK12: omp_if.then:
@@ -12919,13 +12919,13 @@ int main() {
// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39
// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39
+// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39
// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39
-// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39
+// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !39
// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then5:
@@ -12960,13 +12960,13 @@ int main() {
// CHECK12-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
// CHECK12-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
-// CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP24:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL10:%.*]] = trunc i8 [[TMP24]] to i1
// CHECK12-NEXT: [[CONV12:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED11]] to i8*
// CHECK12-NEXT: [[FROMBOOL13:%.*]] = zext i1 [[TOBOOL10]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL13]], i8* [[CONV12]], align 1
// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED11]], align 8
-// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL14:%.*]] = trunc i8 [[TMP26]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE16:%.*]]
// CHECK12: omp_if.then15:
@@ -13034,7 +13034,7 @@ int main() {
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -13162,7 +13162,7 @@ int main() {
// CHECK12-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
@@ -13637,7 +13637,7 @@ int main() {
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[ARG_ADDR]] to i32*
-// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -13700,7 +13700,7 @@ int main() {
// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59
// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !59
+// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !59
// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK12: omp_if.then:
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
index 935fa2fdc3a11..59171d40b5d94 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
@@ -362,7 +362,7 @@ int main() {
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK1-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -416,7 +416,7 @@ int main() {
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18
+// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
@@ -1189,7 +1189,7 @@ int main() {
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42
+// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
@@ -1598,7 +1598,7 @@ int main() {
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK2-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -1652,7 +1652,7 @@ int main() {
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18
+// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
@@ -2425,7 +2425,7 @@ int main() {
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42
+// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
@@ -3532,7 +3532,7 @@ int main() {
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK5-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -3586,7 +3586,7 @@ int main() {
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18
+// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
@@ -4350,7 +4350,7 @@ int main() {
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42
+// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
@@ -4768,7 +4768,7 @@ int main() {
// CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i8*
-// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK6-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
// CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
@@ -4822,7 +4822,7 @@ int main() {
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18
+// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !18
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
@@ -5586,7 +5586,7 @@ int main() {
// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42
+// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1, !llvm.access.group !42
// CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32
// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
index c62b4386594ff..7d2b99806b867 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
@@ -9621,7 +9621,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -9678,7 +9678,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -9709,7 +9709,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK13-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -10136,7 +10136,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK13-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -10222,7 +10222,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -10313,7 +10313,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -10860,7 +10860,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -10922,7 +10922,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -10982,7 +10982,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -11230,7 +11230,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK13-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK13-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -11292,7 +11292,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK13-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -11352,7 +11352,7 @@ int main (int argc, char **argv) {
// CHECK13-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -12280,7 +12280,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -12337,7 +12337,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -12368,7 +12368,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK14-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -12795,7 +12795,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK14-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -12881,7 +12881,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -12972,7 +12972,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -13519,7 +13519,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -13581,7 +13581,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -13641,7 +13641,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -13889,7 +13889,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK14-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK14-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK14-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -13951,7 +13951,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK14-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -14011,7 +14011,7 @@ int main (int argc, char **argv) {
// CHECK14-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK14-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -14939,7 +14939,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -14996,7 +14996,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -15027,7 +15027,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK15-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -15454,7 +15454,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK15-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -15540,7 +15540,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK15-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -15631,7 +15631,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -16178,7 +16178,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -16240,7 +16240,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -16300,7 +16300,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -16548,7 +16548,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK15-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK15-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -16610,7 +16610,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK15-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -16670,7 +16670,7 @@ int main (int argc, char **argv) {
// CHECK15-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK15-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK15-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -17598,7 +17598,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -17655,7 +17655,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_COMB_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -17686,7 +17686,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !28
+// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !28
// CHECK16-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !28
@@ -18113,7 +18113,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK16-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -18199,7 +18199,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
-// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !40
+// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP20]], i32* [[CONV7]], align 4, !llvm.access.group !40
// CHECK16-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !40
@@ -18290,7 +18290,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -18837,7 +18837,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -18899,7 +18899,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !58
+// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !58
// CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !58
@@ -18959,7 +18959,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
// CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP3]])
@@ -19207,7 +19207,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
// CHECK16-NEXT: [[CONV:%.*]] = bitcast i64* [[M_ADDR]] to i32*
// CHECK16-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK16-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -19269,7 +19269,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
-// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !70
+// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
// CHECK16-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !70
// CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !70
@@ -19329,7 +19329,7 @@ int main (int argc, char **argv) {
// CHECK16-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK16-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
// CHECK16-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
diff --git a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp
index 7e95a42396ea5..245bcc0af26cc 100644
--- a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp
@@ -380,8 +380,8 @@ int main (int argc, char **argv) {
// CHECK1-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], i32* [[CONV3]], [100 x i32]* [[TMP1]])
// CHECK1-NEXT: ret void
@@ -789,8 +789,8 @@ int main (int argc, char **argv) {
// CHECK2-NEXT: [[TMP1:%.*]] = load [100 x i32]*, [100 x i32]** [[A_ADDR]], align 8
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[I_ADDR]] to i32*
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[N_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, [100 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]], i32* [[CONV3]], [100 x i32]* [[TMP1]])
// CHECK2-NEXT: ret void
@@ -4329,7 +4329,7 @@ int main (int argc, char **argv) {
// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK21-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
-// CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then:
@@ -4551,7 +4551,7 @@ int main (int argc, char **argv) {
// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK22-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
-// CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK22-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK22: omp_if.then:
@@ -4773,7 +4773,7 @@ int main (int argc, char **argv) {
// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then:
@@ -4993,7 +4993,7 @@ int main (int argc, char **argv) {
// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
-// CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK24-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK24: omp_if.then:
@@ -5991,8 +5991,8 @@ int main (int argc, char **argv) {
// CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK33-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK33-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK33-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK33-NEXT: ret void
@@ -6369,8 +6369,8 @@ int main (int argc, char **argv) {
// CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK34-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK34-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK34-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK34-NEXT: ret void
@@ -7321,7 +7321,7 @@ int main (int argc, char **argv) {
// CHECK37-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK37-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK37-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK37-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK37-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK37-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -7399,7 +7399,7 @@ int main (int argc, char **argv) {
// CHECK37-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK37-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK37-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
-// CHECK37-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK37-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK37-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK37-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK37: omp_if.then:
@@ -7552,8 +7552,8 @@ int main (int argc, char **argv) {
// CHECK37-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK37-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK37-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK37-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK37-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK37-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK37-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK37-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK37-NEXT: ret void
@@ -7764,7 +7764,7 @@ int main (int argc, char **argv) {
// CHECK38-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK38-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK38-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK38-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK38-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK38-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
@@ -7842,7 +7842,7 @@ int main (int argc, char **argv) {
// CHECK38-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK38-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK38-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
-// CHECK38-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8
+// CHECK38-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK38-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK38-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK38: omp_if.then:
@@ -7995,8 +7995,8 @@ int main (int argc, char **argv) {
// CHECK38-NEXT: [[CONV:%.*]] = bitcast i64* [[TE_ADDR]] to i32*
// CHECK38-NEXT: [[CONV1:%.*]] = bitcast i64* [[TH_ADDR]] to i32*
// CHECK38-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
-// CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
-// CHECK38-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK38-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK38-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK38-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]])
// CHECK38-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP1]])
// CHECK38-NEXT: ret void
@@ -8281,7 +8281,7 @@ int main (int argc, char **argv) {
// CHECK39-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK39-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK39-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
-// CHECK39-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK39-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK39-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK39-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK39: omp_if.then:
@@ -8713,7 +8713,7 @@ int main (int argc, char **argv) {
// CHECK40-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
// CHECK40-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
// CHECK40-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
-// CHECK40-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 4
+// CHECK40-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 1
// CHECK40-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK40-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK40: omp_if.then:
diff --git a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp
index fbf312e5e3126..ec700b36af04d 100644
--- a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp
@@ -2571,7 +2571,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -2627,7 +2627,7 @@ int main (int argc, char **argv) {
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
@@ -3540,7 +3540,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
@@ -3596,7 +3596,7 @@ int main (int argc, char **argv) {
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
-// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
diff --git a/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp
index 36d65ef6e9841..e04322d0eaafa 100644
--- a/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp
@@ -348,11 +348,11 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -449,7 +449,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -461,9 +461,9 @@ int main() {
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -706,7 +706,7 @@ int main() {
// CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -806,7 +806,7 @@ int main() {
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1154,11 +1154,11 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1255,7 +1255,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -1267,9 +1267,9 @@ int main() {
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
-// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5
+// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -1512,7 +1512,7 @@ int main() {
// CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
// CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1612,7 +1612,7 @@ int main() {
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]]
@@ -4778,7 +4778,7 @@ int main() {
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -4787,7 +4787,7 @@ int main() {
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -4852,10 +4852,10 @@ int main() {
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
-// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
-// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -5042,7 +5042,7 @@ int main() {
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
@@ -5051,7 +5051,7 @@ int main() {
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -5116,10 +5116,10 @@ int main() {
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
-// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4
+// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4
// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
-// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4
+// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
diff --git a/clang/test/OpenMP/teams_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_firstprivate_codegen.cpp
index 7ec4418794e3c..1df54320269a4 100644
--- a/clang/test/OpenMP/teams_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/teams_firstprivate_codegen.cpp
@@ -180,7 +180,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -206,7 +206,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK1-NEXT: store i32 1, i32* [[G1]], align 128
-// CHECK1-NEXT: store i32 2, i32* [[CONV]], align 8
+// CHECK1-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK1-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -245,7 +245,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -271,7 +271,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128
// CHECK2-NEXT: store i32 1, i32* [[G1]], align 128
-// CHECK2-NEXT: store i32 2, i32* [[CONV]], align 8
+// CHECK2-NEXT: store i32 2, i32* [[CONV]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
// CHECK2-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
@@ -578,11 +578,11 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -639,14 +639,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
-// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8
+// CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
@@ -711,7 +711,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
-// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
@@ -1309,11 +1309,11 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
// CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
+// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
@@ -1370,14 +1370,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
// CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0
// CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4
// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0
// CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
// CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8*
// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false)
-// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8
+// CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 4
// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
// CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2
@@ -1442,7 +1442,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
-// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
diff --git a/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected b/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected
index 03e0f8ef60e07..7cc6b0dae4d47 100644
--- a/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected
+++ b/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected
@@ -32,7 +32,7 @@ void foo(int a)
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
-// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
// CHECK-NEXT: call void @use(i32 [[TMP0]])
// CHECK-NEXT: ret void
//
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