[PATCH] D113237: [RISCV] Support Zifencei extension

Shao-Ce SUN via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Sun Dec 5 19:09:18 PST 2021


achieveartificialintelligence updated this revision to Diff 391951.
achieveartificialintelligence added a comment.
Herald added subscribers: cfe-commits, jdoerfert, rupprecht, emaste, qcolombet.
Herald added a reviewer: jhenderson.
Herald added a reviewer: MaskRay.
Herald added a project: clang.

Update I-ext to Version 2.1


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113237/new/

https://reviews.llvm.org/D113237

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Driver/riscv-cpus.c
  lld/test/ELF/riscv-attributes.s
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
  llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
  llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/attribute-with-insts.s
  llvm/test/MC/RISCV/attribute-with-option.s
  llvm/test/MC/RISCV/attribute.s
  llvm/test/MC/RISCV/csr-aliases.s
  llvm/test/MC/RISCV/deprecated-csr-names.s
  llvm/test/MC/RISCV/invalid-attribute.s
  llvm/test/MC/RISCV/machine-csr-names.s
  llvm/test/MC/RISCV/rv32-machine-csr-names.s
  llvm/test/MC/RISCV/rv32-user-csr-names.s
  llvm/test/MC/RISCV/rv32e-valid.s
  llvm/test/MC/RISCV/rv32i-aliases-valid.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32i-valid.s
  llvm/test/MC/RISCV/rv32zicsr-invalid.s
  llvm/test/MC/RISCV/rv32zicsr-valid.s
  llvm/test/MC/RISCV/rv32zifencei-valid.s
  llvm/test/MC/RISCV/rv64-machine-csr-names.s
  llvm/test/MC/RISCV/rv64-user-csr-names.s
  llvm/test/MC/RISCV/rvf-aliases-valid.s
  llvm/test/MC/RISCV/rvf-user-csr-names.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/test/MC/RISCV/rvv-user-csr-names.s
  llvm/test/MC/RISCV/rvzicsr-aliases-valid.s
  llvm/test/MC/RISCV/supervisor-csr-names.s
  llvm/test/MC/RISCV/user-csr-names.s
  llvm/test/tools/llvm-objdump/ELF/RISCV/unknown-arch-attr.test
  llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s

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