[PATCH] D112398: [RISCV] Add ABI testing for Float16.

Kito Cheng via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Thu Nov 11 02:55:35 PST 2021

kito-cheng added a comment.
Herald added subscribers: VincentWu, luke957.

>From the psABI aspect, we already included that by this PR <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/172>, this PR added size and alignment for `_Float16`, and we didn't added extra rule for that, because we believe that's already covered by existing rule:


For soft float ABI (ilp32/lp64):

  Floating-point reals are passed the same way as aggregates of the same size, complex floating-point numbers are passed the same way as a struct containing two floating-point reals. (This constraint changes when the integer calling convention is augmented by the hardware floating-point calling convention.)

-> `_Float16` following same rule as float, pass argument and return value in GPR.


For hard float ABI (ilp32f/lp64f/ilp32d/lp64d):

  A real floating-point argument is passed in a floating-point argument register if it is no more than FLEN bits wide and at least one floating-point argument register is available. Otherwise, it is passed according to the integer calling convention. When a floating-point argument narrower than FLEN bits is passed in a floating-point register, it is 1-extended (NaN-boxed) to FLEN bits.

-> `_Float16` following same rule as float, pass argument and return value in FPR.


So basically same as @rogfer01's understanding and the rule is same between w/ and w/o zfh.

@jrtc27 could you take a look for this revision?

  rG LLVM Github Monorepo



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