[PATCH] D113638: [xray] Add support for hexagon architecture

[Brian Cain via Phabricator via cfe-commits]

androm3da added a comment.

This patch spans several areas, so I would be happy to decompose it into smaller parts if it made it easier for reviewers.



================
Comment at: compiler-rt/lib/xray/xray_hexagon.cpp:76-84
+static void WriteInstFlushCache(void *Addr, uint32_t NewInstruction) {
+  asm volatile("icinva(%[inst_addr])\n\t"
+               "isync\n\t"
+               "memw(%[inst_addr]) = %[new_inst]\n\t"
+               "dccleaninva(%[inst_addr])\n\t"
+               "syncht\n\t"
+               :
----------------
If we need to support cases where the entire sled spans cache lines, then we must iterate over the icinva() instead.



================
Comment at: compiler-rt/lib/xray/xray_hexagon.cpp:76-84
+static void WriteInstFlushCache(void *Addr, uint32_t NewInstruction) {
+  asm volatile("icinva(%[inst_addr])\n\t"
+               "isync\n\t"
+               "memw(%[inst_addr]) = %[new_inst]\n\t"
+               "dccleaninva(%[inst_addr])\n\t"
+               "syncht\n\t"
+               :
----------------
androm3da wrote:
> If we need to support cases where the entire sled spans cache lines, then we must iterate over the icinva() instead.
> 
Other arches do atomic stores.  I think we will need to change this to: LL first, then icinva/isync, then SC.  

If the SC fails then either we re-run all those steps because we want to clobber it or we do nothing because we assume some other thread applied the same patch first?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113638/new/

https://reviews.llvm.org/D113638