[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.


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Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c:3
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x -target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
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eopXD wrote:
> craig.topper wrote:
> > Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x imply zve32x?
> Just added D113336 to resolve this. I will rebase this patch and change test cases.
Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112613/new/

https://reviews.llvm.org/D112613