[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:112
     return 0;
-  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+  assert(RVVVectorBitsMax >= 32 && RVVVectorBitsMax <= 65536 &&
          isPowerOf2_32(RVVVectorBitsMax) &&
----------------
HsiangKai wrote:
> craig.topper wrote:
> > The max should be greater than ZvlLen right?
> Should it be less than or equal to ZvlLen? I would suggest to return 0 when `RVVVectorBitsMax > ZvlLen`.
> The value also needs to `>= 64`.
@HsiangKai I think you mis-typed the equation? It should be `RVVVectorBitsMax < ZvlLen` ;)




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694