[PATCH] D112600: [ARM] Use hardware TLS register in Thumb2 mode when -mtp=cp15 is passed

[Ard Biesheuvel via Phabricator via cfe-commits]

ardb added inline comments.


================
Comment at: clang/test/CodeGen/arm-tphard.c:10
+}
+
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nickdesaulniers wrote:
> Let's make this a test under llvm/test/CodeGen/, using IR:
> ```
> ; RUN: llc --mtriple=armv7-linux-gnueabihf -o - %s | FileCheck %s
> ; RUN: llc --mtriple=thumbv7-linux-gnu -o - %s | FileCheck %s
> define dso_local i8* @tphard() "target-features"="+read-tp-hard" {
> // CHECK-NOT: __aeabi_read_tp
>   %1 = tail call i8* @llvm.thread.pointer()
>   ret i8* %1
> }
> 
> declare i8* @llvm.thread.pointer()
> ```
> 
> Let's make this a test under llvm/test/CodeGen/, using IR:

Why is that better?

> ```
> ; RUN: llc --mtriple=armv7-linux-gnueabihf -o - %s | FileCheck %s
> ; RUN: llc --mtriple=thumbv7-linux-gnu -o - %s | FileCheck %s

Are you sure using this triple forces generation of Thumb2 code? It didn't seem to when I tried.

> define dso_local i8* @tphard() "target-features"="+read-tp-hard" {
> // CHECK-NOT: __aeabi_read_tp

Are you sure __aeabi_read_tp will appear in the IR for soft TP?

>   %1 = tail call i8* @llvm.thread.pointer()
>   ret i8* %1
> }
> 
> declare i8* @llvm.thread.pointer()
> ```
> 




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  https://reviews.llvm.org/D112600/new/

https://reviews.llvm.org/D112600