[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5003
+        N->getConstantOperandVal(1) == Intrinsic::ppc_tw) {
+      int16_t SImm;
+      if (isIntS16Immediate(N->getOperand(3), SImm)) {
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I think a couple of improvements can be made here:
1. Populate the `Opcode` and `Ops` array based on various conditions and add a single call to `SelectNodeTo()`
2. Handle the first input being constant (and then flip the condition)


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Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:131
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tdi 3, 3, 32767
+; CHECK-NEXT:    blr
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Can we add `-ppc-asm-full-reg-names` to the RUN lines so it is more clear which operand is a register and which is an immediate. This works on AIX now since https://reviews.llvm.org/D94282 landed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112285/new/

https://reviews.llvm.org/D112285