[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence marked 6 inline comments as done.
achieveartificialintelligence added inline comments.


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Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:164
 
+static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                              uint64_t Address,
----------------
MaskRay wrote:
> Use `functionName`.
> 
> There is inconsistency in the code base but `functionName` is used much more than `FunctionName`.
I fix this in D112520


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:539
 
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
----------------
jrtc27 wrote:
> This needs to be coordinated with D95588; you both define GPR pairs for RV32 but in different ways. There needs to be only one.
After D95588 is accepted, we will reuse this.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298