[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: achieveartificialintelligence, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
eopXD requested review of this revision.
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Herald added projects: clang, LLVM.

This patch is still a WIP and should be reviewed together with following patches once everything is complete.

`zve` is the new standard vector extension to specify varying degrees of vector support for embedding processors.
The `zve` extension is related to the `zvl` extension and other updates that are added in v1.0-rc2.

Clang defines macro `__riscv_v_max_eew` for `zve` and it can be used for applications that uses the vector extension.
Clang defines macro `__riscv_v_max_eew_fp` for `zve` and it can be used for applications that uses the vector extension.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112408

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/add.s
  llvm/test/MC/RISCV/rvv/and.s
  llvm/test/MC/RISCV/rvv/clip.s
  llvm/test/MC/RISCV/rvv/compare.s
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/div.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/fadd.s
  llvm/test/MC/RISCV/rvv/fcompare.s
  llvm/test/MC/RISCV/rvv/fdiv.s
  llvm/test/MC/RISCV/rvv/fmacc.s
  llvm/test/MC/RISCV/rvv/fminmax.s
  llvm/test/MC/RISCV/rvv/fmul.s
  llvm/test/MC/RISCV/rvv/fmv.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/freduction.s
  llvm/test/MC/RISCV/rvv/fsub.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/macc.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/minmax.s
  llvm/test/MC/RISCV/rvv/mul.s
  llvm/test/MC/RISCV/rvv/mv.s
  llvm/test/MC/RISCV/rvv/or.s
  llvm/test/MC/RISCV/rvv/others.s
  llvm/test/MC/RISCV/rvv/reduction.s
  llvm/test/MC/RISCV/rvv/shift.s
  llvm/test/MC/RISCV/rvv/sign-injection.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/sub.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/xor.s

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