[clang] 4fc2f49 - [PowerPC] Fix __builtin_ppc_load2r to return short instead of int.
Stefan Pintilie via cfe-commits
cfe-commits at lists.llvm.org
Mon Oct 4 04:17:09 PDT 2021
Author: Stefan Pintilie
Date: 2021-10-04T06:17:02-05:00
New Revision: 4fc2f4979cf56fdc87cbd5ed1b02ef3461916731
URL: https://github.com/llvm/llvm-project/commit/4fc2f4979cf56fdc87cbd5ed1b02ef3461916731
DIFF: https://github.com/llvm/llvm-project/commit/4fc2f4979cf56fdc87cbd5ed1b02ef3461916731.diff
LOG: [PowerPC] Fix __builtin_ppc_load2r to return short instead of int.
This patch fixes the return value of the builtin __builtin_ppc_load2r to
correctly return short instead of int.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D110771
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index 65f490a214bcb..3fa5729fc7d03 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -121,7 +121,7 @@ BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
// load
-BUILTIN(__builtin_ppc_load2r, "UiUs*", "")
+BUILTIN(__builtin_ppc_load2r, "UsUs*", "")
BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
// store
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index c7dcde149a157..91d90d7ba5f7f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15655,6 +15655,12 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
Value *Rotate = Builder.CreateCall(F, {Ops[0], Ops[0], ShiftAmt});
return Builder.CreateAnd(Rotate, Ops[2]);
}
+ case PPC::BI__builtin_ppc_load2r: {
+ Function *F = CGM.getIntrinsic(Intrinsic::ppc_load2r);
+ Ops[0] = Builder.CreateBitCast(Ops[0], Int8PtrTy);
+ Value *LoadIntrinsic = Builder.CreateCall(F, Ops);
+ return Builder.CreateTrunc(LoadIntrinsic, Int16Ty);
+ }
// FMA variations
case PPC::BI__builtin_vsx_xvmaddadp:
case PPC::BI__builtin_vsx_xvmaddasp:
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c b/clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
index e0ca6fdfe62a5..c95bc473e5d5b 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
@@ -1,4 +1,4 @@
-// REQUIRES: powerpc-registered-target.
+// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index d4f1e5e985b22..e60bad8fd9f0c 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1629,8 +1629,7 @@ let TargetPrefix = "ppc" in {
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
// load
def int_ppc_load2r
- : GCCBuiltin<"__builtin_ppc_load2r">,
- Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
+ : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
def int_ppc_load4r
: GCCBuiltin<"__builtin_ppc_load4r">,
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 6b0b6397ba609..d9c9930922f70 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15681,6 +15681,18 @@ void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known.Zero = ~1U; // All bits but the low one are known to be zero.
break;
}
+ break;
+ }
+ case ISD::INTRINSIC_W_CHAIN: {
+ switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
+ default:
+ break;
+ case Intrinsic::ppc_load2r:
+ // Top bits are cleared for load2r (which is the same as lhbrx).
+ Known.Zero = 0xFFFF0000;
+ break;
+ }
+ break;
}
}
}
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
index 7216c12d41629..ed3a96f8dd4c8 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
@@ -52,12 +52,28 @@ declare void @llvm.ppc.store4r(i32, i8*)
define dso_local zeroext i16 @test_builtin_ppc_load2r() {
; CHECK-64B-LABEL: test_builtin_ppc_load2r:
; CHECK-64B: lhbrx 3, 0, 3
-; CHECK-64B-NEXT: clrldi 3, 3, 48
; CHECK-64B-NEXT: blr
; CHECK-32B-LABEL: test_builtin_ppc_load2r:
; CHECK-32B: lhbrx 3, 0, 3
-; CHECK-32B-NEXT: clrlwi 3, 3, 16
+; CHECK-32B-NEXT: blr
+entry:
+ %0 = load i16*, i16** @us_addr, align 8
+ %1 = bitcast i16* %0 to i8*
+ %2 = call i32 @llvm.ppc.load2r(i8* %1)
+ %conv = trunc i32 %2 to i16
+ ret i16 %conv
+}
+
+define dso_local signext i16 @test_builtin_ppc_load2r_signext() {
+; CHECK-64B-LABEL: test_builtin_ppc_load2r_signext:
+; CHECK-64B: lhbrx 3, 0, 3
+; CHECK-64B-NEXT: extsh 3, 3
+; CHECK-64B-NEXT: blr
+
+; CHECK-32B-LABEL: test_builtin_ppc_load2r_signext:
+; CHECK-32B: lhbrx 3, 0, 3
+; CHECK-32B-NEXT: extsh 3, 3
; CHECK-32B-NEXT: blr
entry:
%0 = load i16*, i16** @us_addr, align 8
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