[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via cfe-commits]

Jim marked 7 inline comments as done.
Jim added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909
+
+// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on RV64.
+let DecoderNamespace = "RISCV32Zpsfoperand_",
----------------
jrtc27 wrote:
> Having the same instruction in two different extensions under two different names is insane. Currently this implementation lets you use the "wrong" name for kmar64 with Zpn. But I would prefer the spec weren't crazy.
I am still working on fixing it (from spec or ...) . But it is spec issue.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:228
+
+def GPR32Pair : RegisterClass<"RISCV", [untyped], 64, (add GPR32Pairs)> {
+  let Size = 64;
----------------
jrtc27 wrote:
> Why is this untyped?
GPR32Pair has untyped type. 
In code generation, It captures some operation with i64 type supported by Zpsoperand to untyped during legalization. 
In my mind, untyped is used to be represented special type don't need any legalization.
I refer to ARMRegisterInfo.td that defines GPRPair with untyped.


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https://reviews.llvm.org/D95588