[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim Lin via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Fri Sep 10 20:14:33 PDT 2021


Jim updated this revision to Diff 372052.
Jim added a comment.

Update to the newest P spec 0.96
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#revision-history

1. Merger Zprvsfextra (sub-extension for RV64 only) into Zpn So, RV32 and RV64 have the same sub-extension combination policy. P = Zpn + Zpsfoperand @jrtc27's concern is not existed now.
2. Removed CLO* instructions.
3. Fix incorrect testcases.

1. CHECK: attribute      5, "rv64i2p0_p0p93_zpn0p96_zprvsfextra0p96_zpsfoperand0p96"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/rv32zpn-invalid.s
  llvm/test/MC/RISCV/rv32zpsfoperand-invalid.s
  llvm/test/MC/RISCV/rv32zpsfoperand-valid.s
  llvm/test/MC/RISCV/rv64zpn-invalid.s
  llvm/test/MC/RISCV/rv64zpn-valid.s
  llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s
  llvm/test/MC/RISCV/rv64zpsfoperand-valid.s
  llvm/test/MC/RISCV/rvp-invalid.s
  llvm/test/MC/RISCV/rvp-non-simd-valid.s
  llvm/test/MC/RISCV/rvp-partial-simd-valid.s
  llvm/test/MC/RISCV/rvp-simd-alu-valid.s
  llvm/test/MC/RISCV/rvp-simd-cmp-valid.s
  llvm/test/MC/RISCV/rvp-simd-misc-valid.s
  llvm/test/MC/RISCV/rvp-simd-mul-valid.s
  llvm/test/MC/RISCV/rvp-simd-shift-valid.s
  llvm/test/MC/RISCV/rvp-simd-unpacking-valid.s

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