[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Aug 26 17:00:51 PDT 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/X86/X86InstrFoldTables.cpp:1852
+ { X86::VFCMULCPHZrr, X86::VFCMULCPHZrm, 0 },
+ { X86::VFCMULCSHZrr, X86::VFCMULCSHZrm, TB_NO_REVERSE },
{ X86::VFMADDPD4Yrr, X86::VFMADDPD4Ymr, 0 },
----------------
LuoYuanke wrote:
> pengfei wrote:
> > LuoYuanke wrote:
> > > Why FR32X version is not needed for complex scalar instructions?
> > Do you mean complex ss/sd? We don't have these instructions.
> No, I mean we have both X86::XXX and X86::XXX_Int for other instructions. One is FR16X which can be unfolded, one is VR128X which can't. For example, VFNMADD213SHZm and VFNMADD213SHZm_Int.
The VFCMULCSHZrr instructions produce two 16-bit values packed into the lower 32 bits. That would mean we would need a FR32X result, but it couldn't interact meaningfully with any other FR32X instruction since its really two values.
I think we only have FR32/FR64 instructions for things that have generic IR equivalents or that we create from other generic IR operations. Like I think we have an FR32 RCP and RSQRT because we can convert float div or 1/sqrt to them.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105269/new/
https://reviews.llvm.org/D105269
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