[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.


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Comment at: clang/test/Sema/inline-asm-validate-riscv.c:27-28
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with asm clobber list}}
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I don't really understand the point of erroring-out in these two cases where the register is an input and is also clobbered. In fact, I've run into a case where that would be useful and accurately reflected the situation. But GCC's documentation explicitly prohibits that. I'm not sure if there's a fundamental reason for that, or if it's just an implementation quirk.


Repository:
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  https://reviews.llvm.org/D108624/new/

https://reviews.llvm.org/D108624