[clang] 8930af4 - [PowerPC] Implement XL compatibility builtin __addex
Lei Huang via cfe-commits
cfe-commits at lists.llvm.org
Thu Aug 12 14:38:26 PDT 2021
Author: Lei Huang
Date: 2021-08-12T16:38:21-05:00
New Revision: 8930af45c35b5224d3b90c8408957f6b7bfa1be0
URL: https://github.com/llvm/llvm-project/commit/8930af45c35b5224d3b90c8408957f6b7bfa1be0
DIFF: https://github.com/llvm/llvm-project/commit/8930af45c35b5224d3b90c8408957f6b7bfa1be0.diff
LOG: [PowerPC] Implement XL compatibility builtin __addex
Add builtin and intrinsic for `__addex`.
This patch is part of a series of patches to provide builtins for
compatibility with the XL compiler.
Reviewed By: stefanp, nemanjai, NeHuang
Differential Revision: https://reviews.llvm.org/D107002
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index dfe97af300f41..7a1795d9e550d 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -144,6 +144,7 @@ BUILTIN(__builtin_ppc_mfspr, "ULiIi", "")
BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
BUILTIN(__builtin_ppc_mtspr, "vIiULi", "")
BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
+BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index bf857f58951b3..73217b418e81f 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -9733,6 +9733,9 @@ def err_argument_invalid_range : Error<
def warn_argument_invalid_range : Warning<
"argument value %0 is outside the valid range [%1, %2]">, DefaultError,
InGroup<DiagGroup<"argument-outside-range">>;
+def warn_argument_undefined_behaviour : Warning<
+ "argument value %0 will result in undefined behaviour">,
+ InGroup<DiagGroup<"argument-undefined-behaviour">>;
def err_argument_not_multiple : Error<
"argument should be a multiple of %0">;
def err_argument_not_power_of_2 : Error<
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 839fb93ff3d0c..c15d2df33f9f7 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -236,6 +236,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+ Builder.defineMacro("__addex", "__builtin_ppc_addex");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index d3736311d5662..e5008330a4150 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3294,6 +3294,7 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
case PPC::BI__builtin_ppc_store8r:
case PPC::BI__builtin_ppc_insert_exp:
case PPC::BI__builtin_ppc_extract_sig:
+ case PPC::BI__builtin_ppc_addex:
return true;
}
return false;
@@ -3435,6 +3436,19 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
case PPC::BI__builtin_ppc_insert_exp:
return SemaFeatureCheck(*this, TheCall, "power9-vector",
diag::err_ppc_builtin_only_on_arch, "9");
+ case PPC::BI__builtin_ppc_addex: {
+ if (SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+ diag::err_ppc_builtin_only_on_arch, "9") ||
+ SemaBuiltinConstantArgRange(TheCall, 2, 0, 3))
+ return true;
+ // Output warning for reserved values 1 to 3.
+ int ArgValue =
+ TheCall->getArg(2)->getIntegerConstantExpr(Context)->getSExtValue();
+ if (ArgValue != 0)
+ Diag(TheCall->getBeginLoc(), diag::warn_argument_undefined_behaviour)
+ << ArgValue;
+ return false;
+ }
case PPC::BI__builtin_ppc_mtfsb0:
case PPC::BI__builtin_ppc_mtfsb1:
return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
index 741e87194a7d4..50d5aefdd2941 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
@@ -80,3 +80,19 @@ double insert_exp (double d, unsigned long long ull) {
// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
return __insert_exp (d, ull);
}
+
+signed long long test_builtin_ppc_addex0() {
+ // CHECK-LABEL: @test_builtin_ppc_addex0
+ // CHECK: %2 = call i64 @llvm.ppc.addex(i64 %0, i64 %1, i32 0)
+ // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+ // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
+ return __builtin_ppc_addex(sll, sll, 0);
+}
+
+unsigned long long test_builtin_ppc_addex1() {
+ // CHECK-LABEL: @test_builtin_ppc_addex1
+ // CHECK: %2 = call i64 @llvm.ppc.addex(i64 %0, i64 %1, i32 0)
+ // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+ // CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
+ return __builtin_ppc_addex(ull, ull, 0);
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
index 2d7449f4f1318..795e05a40e15d 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
// RUN: -fsyntax-only -Wall -Werror -verify %s
extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
void test_builtin_ppc_cmprb() {
int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
}
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_addex() {
+ long long res = __builtin_ppc_addex(ll, ll, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
+ unsigned long long res2 = __builtin_ppc_addex(ull, ull, -1); // expected-error {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+#endif
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
new file mode 100644
index 0000000000000..0a01e5b42b8cb
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN: -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+ long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will result in undefined behaviour}}
+ unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will result in undefined behaviour}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 92d3bdea37edf..f39ec573c6332 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@ let TargetPrefix = "ppc" in {
def int_ppc_fres
: GCCBuiltin<"__builtin_ppc_fres">,
Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-
+ def int_ppc_addex
+ : GCCBuiltin<"__builtin_ppc_addex">,
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<2>>]>;
def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty,
llvm_double_ty], [IntrNoMem]>;
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 76663acf47829..fe7487ad3d004 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@ def : InstRW<[],
DCBI,
DCCCI,
ICCCI,
- ADDEX
+ ADDEX,
+ ADDEX8
)> { let Unsupported = 1; }
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 92712c5c072b4..405cfe33ac201 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@ def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs),
"hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
}
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+ (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+ "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+ [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+ timm:$CY))]>;
+
//===----------------------------------------------------------------------===//
// Instruction Patterns
//
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
index 30d4885903dd8..7aa8b0e7e8327 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,14 @@ entry:
ret double %0
}
declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addex 3, 3, 4, 0
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
More information about the cfe-commits
mailing list