[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

[Pengfei Wang via Phabricator via cfe-commits]

pengfei updated this revision to Diff 363946.
pengfei added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105263/new/

https://reviews.llvm.org/D105263

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/docs/LanguageExtensions.rst
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/avx512fp16intrin.h
  clang/lib/Headers/avx512vlfp16intrin.h
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/test/CodeGen/X86/avx512fp16-abi.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vlfp16-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/predefined-arch-macros.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
  llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
  llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86CallingConv.td
  llvm/lib/Target/X86/X86FastISel.cpp
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrVecCompiler.td
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/lib/Target/X86/X86Schedule.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll
  llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16.ll
  llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16.ll
  llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16.ll
  llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
  llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
  llvm/test/CodeGen/X86/avx512fp16-insert-extract.ll
  llvm/test/CodeGen/X86/avx512fp16-mov.ll
  llvm/test/CodeGen/X86/avx512fp16-mscatter.ll
  llvm/test/CodeGen/X86/avx512fp16-subv-broadcast-fp16.ll
  llvm/test/CodeGen/X86/avx512fp16vl-intrinsics.ll
  llvm/test/CodeGen/X86/fp128-cast-strict.ll
  llvm/test/CodeGen/X86/pseudo_cmov_lower-fp16.ll
  llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
  llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
  llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
  llvm/test/MC/Disassembler/X86/avx512fp16.txt
  llvm/test/MC/X86/avx512fp16.s
  llvm/test/MC/X86/intel-syntax-avx512fp16.s
  llvm/test/MachineVerifier/test_copy_physregs_x86.mir
  llvm/utils/TableGen/X86DisassemblerTables.cpp
  llvm/utils/TableGen/X86DisassemblerTables.h
  llvm/utils/TableGen/X86RecognizableInstr.cpp
  llvm/utils/TableGen/X86RecognizableInstr.h

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