[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.
Jianjian Guan via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Sun Aug 1 20:37:38 PDT 2021
jacquesguan added inline comments.
================
Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:179
const std::vector<int64_t> &IntrinsicTypes,
- StringRef RequiredExtension, unsigned NF);
+ const std::vector<StringRef> RequiredExtensions, unsigned NF);
~RVVIntrinsic() = default;
----------------
craig.topper wrote:
> RequiredExtensions should be a reference
Done, thanks.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:349
+ if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
+ errs() << "The V extension does not support EEW=64 for index values "
+ "when XLEN=32\n";
----------------
craig.topper wrote:
> This would just print a message to stderr but wouldn't fail the program. Probably should use report_fatal_error. Or we could let the caller go to SelectCode which would also trigger a "Cannot select" fatal error.
Done, thanks.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:430
+ if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
+ errs() << "The V extension does not support EEW=64 for index values "
+ "when XLEN=32\n";
----------------
craig.topper wrote:
> Same as above
Done, thanks.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106518/new/
https://reviews.llvm.org/D106518
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