[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;
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Jim wrote:
> jrtc27 wrote:
> > Jim wrote:
> > > Jim wrote:
> > > > luismarques wrote:
> > > > > jrtc27 wrote:
> > > > > > This assumes RV32, and is not clear it applies to register pairs
> > > > > What's the best way to address this?
> > > > sub_lo and sub_hi are only used for GPRPair register class to extract a register from pair registers on RV32.
> > > Do you mean that sub_lo and sub_hi only used on RV32? Does it need to rename or ..?
> > Yes, these should have names that make it clear they're for each half of a 2*32-bit register pair. Otherwise it sounds like they're the 32-bit hi and lo halves of the 64-bit registers on RV64.
> Rename it to gpr_pair_lo and gpr_pair_hi
The names still do not reflect the fact that they are only for RV32; currently it *looks* like on RV64 it'd give you the 64-bit GPR


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  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588