[PATCH] D107082: [X86][RFC] Enable `_Float16` type support on X86 following the psABI
Pengfei Wang via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jul 29 19:37:37 PDT 2021
pengfei updated this revision to Diff 362958.
pengfei added a comment.
Remove unused vector f16 definitions.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107082/new/
https://reviews.llvm.org/D107082
Files:
clang/docs/LanguageExtensions.rst
clang/docs/ReleaseNotes.rst
clang/lib/Basic/Targets/X86.cpp
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/X86/fp16-abi.c
clang/test/Sema/Float16.c
clang/test/Sema/conversion-target-dep.c
clang/test/SemaCXX/Float16.cpp
llvm/docs/ReleaseNotes.rst
llvm/include/llvm/IR/RuntimeLibcalls.def
llvm/include/llvm/Target/TargetSelectionDAG.td
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/X86/X86CallingConv.td
llvm/lib/Target/X86/X86FastISel.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
llvm/test/CodeGen/X86/atomic-non-integer.ll
llvm/test/CodeGen/X86/avx512-insert-extract.ll
llvm/test/CodeGen/X86/avx512-masked_memop-16-8.ll
llvm/test/CodeGen/X86/cvt16.ll
llvm/test/CodeGen/X86/fastmath-float-half-conversion.ll
llvm/test/CodeGen/X86/fmf-flags.ll
llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
llvm/test/CodeGen/X86/freeze.ll
llvm/test/CodeGen/X86/half-constrained.ll
llvm/test/CodeGen/X86/half.ll
llvm/test/CodeGen/X86/pr31088.ll
llvm/test/CodeGen/X86/pr38533.ll
llvm/test/CodeGen/X86/pr47000.ll
llvm/test/CodeGen/X86/shuffle-extract-subvector.ll
llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
llvm/test/CodeGen/X86/vec_fp_to_int.ll
llvm/test/CodeGen/X86/vector-half-conversions.ll
llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
llvm/test/MC/X86/x86_64-asm-match.s
llvm/test/MachineVerifier/test_copy_physregs_x86.mir
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