[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-features'.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/riscv-isa-features.ll:1
+; RUN: llc -o - < %s | FileCheck %s
+; -mattr option would overwrite target-feature and module flag riscv-isa-features
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Use update_llc_test_checks for these.


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Comment at: llvm/test/CodeGen/RISCV/riscv-isa-features.ll:2
+; RUN: llc -o - < %s | FileCheck %s
+; -mattr option would overwrite target-feature and module flag riscv-isa-features
+; RUN: llc -o - -mattr=+f,+d < %s | FileCheck %s -check-prefix=ISA-F-D
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It's not overriding. It's just that #0 doesn't include -f,-d so applying #0 atop the default target-features keeps the default f and d features.


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Comment at: llvm/test/CodeGen/RISCV/riscv-isa-features.ll:3
+; -mattr option would overwrite target-feature and module flag riscv-isa-features
+; RUN: llc -o - -mattr=+f,+d < %s | FileCheck %s -check-prefix=ISA-F-D
+; RUN: llc --filetype=obj -o - < %s | llvm-readelf -A - \
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CHECK and ISA-F-D are not consistent with the check prefixes used in other RISC-V tests.


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Comment at: llvm/test/CodeGen/RISCV/riscv-isa-features.ll:29
+
+attributes #0 = { "target-features"="+64bit,+a,+c,+m"}
+attributes #1 = { "target-features"="+64bit,+a,+c,+d,+f,+m"}
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Space before }


Repository:
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  https://reviews.llvm.org/D106347/new/

https://reviews.llvm.org/D106347