[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

Thu Jul 22 07:32:59 PDT 2021

HsiangKai added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10
 /// This file describes the RISC-V instructions from the standard 'V' Vector
 /// extension, version 0.10.
 /// This version is still experimental as the 'V' extension hasn't been
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frasercrmck wrote:
> khchen wrote:
> > jacquesguan wrote:
> > > khchen wrote:
> > > > Do we need to update 0.10 to 1.0-rc?
> > > > If the answer is yes, I think maybe we also need to update the clang part (ex. arch parsing, predefine macro) in follow-up patches.
> > > > 
> > > > 
> > > Maybe update it after finishing all changes in 1.0-rc?
> > > Maybe update it after finishing all changes in 1.0-rc?
> > Yes.
> > 
> > The other questions like how do you encode `rc1` in `march` or predefined architecture extension macro.
> > or maybe we could just use 1.0 directly because v is still an experiential extension.
> > 
> > @luismarques  @frasercrmck @craig.topper @HsiangKai What do you think?
> Maybe we can discuss in the call today, but my initial thoughts would be to just say 1.0 for the reasons you specified.
> 
> Perhaps there's already precedent in dealing with release-candidate specs for the base ISA or other extensions?
I expect v1.0-rc1 will have no big change, especially for these renaming issues. I vote for 1.0 for the experimental extension.

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https://reviews.llvm.org/D105690