[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

Thu Jul 22 03:30:45 PDT 2021

frasercrmck added inline comments.

================
Comment at: clang/include/clang/Basic/riscv_vector.td:555

+defvar Xlen32EEWList = [["8", "(Log2EEW:3)"],
+                        ["16", "(Log2EEW:4)"],
----------------
jrtc27 wrote:
> Ignoring whether the change is actually correct, this should be capitalised as XLen32EEWList, but really this should actually be RV32 not XLen32 as that's not a term we use.
While we're here I'm wondering whether a top-level `Xlen32EEWList`/`RV32EEWList` is conveying the wrong thing. It's only the loads and stores that have a different EEW list on RV32, isn't it?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518