[PATCH] D94098: [Clang][AArch64] Inline assembly support for the ACLE type 'data512_t'.

[Eli Friedman via Phabricator via cfe-commits]

efriedma added a comment.

In D94098#2886319 <https://reviews.llvm.org/D94098#2886319>, @labrinea wrote:

> Firstly, the information that the load/store comes from an inline asm operand gets lost by the time the SelectionDAG processes those nodes, and so we cannot use a target hook to select a special value type for them (as discussed in D94097 <https://reviews.llvm.org/D94097> we want to narrow down the MVT specialization for an llvm type to only apply to asm operands and not universally).

We don't want a special value for the load/store operations feeding into a inline asm, I think?  For an input, we just want to convert the final insertelement to i64x8, using something like along the lines of REG_SEQUENCE.  This means we won't use an ld64b to load the registers, but I think that's what we want; in general, the input registers won't come from some contiguous hunk of memory.  For example, say someone wrote something like this:

  struct foo { unsigned long long x[8]; };
  void store(int *in, void *addr)
  {
      struct foo x = { in[0], in[1], in[4], in[16], in[25], in[36], in[49], in[64] };
      __asm__ volatile ("st64b %0,[%1]" : : "r" (x), "r" (addr) : "memory" );
  }

Intuitively, I would expect this to compile to a sequence of ldr, followed by st64b.  But you're expecting this should compile to a sequence of ldr, followed by a sequence of stp, followed by an ld64b, followed by an st64b?


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