[clang] de39566 - [PowerPC] Fix popcntb XL Compat Builtin for 32bit
Kamau Bridgeman via cfe-commits
cfe-commits at lists.llvm.org
Thu Jul 15 11:20:12 PDT 2021
Author: Quinn Pham
Date: 2021-07-15T13:19:47-05:00
New Revision: de3956605a701295c928925a3e5096008a8521ba
URL: https://github.com/llvm/llvm-project/commit/de3956605a701295c928925a3e5096008a8521ba
DIFF: https://github.com/llvm/llvm-project/commit/de3956605a701295c928925a3e5096008a8521ba.diff
LOG: [PowerPC] Fix popcntb XL Compat Builtin for 32bit
This patch implements the `__popcntb` XL compatibility builtin for 32bit in the frontend and backend. This patch also updates tests for `__popcntb` and other XL Compat sync related builtins.
Reviewed By: #powerpc, nemanjai, amyk
Differential Revision: https://reviews.llvm.org/D105360
Added:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
Removed:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
################################################################################
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 67f57015e49fd..0635be425e0aa 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15600,6 +15600,12 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
case PPC::BI__builtin_ppc_ldarx:
case PPC::BI__builtin_ppc_lwarx:
return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+ case PPC::BI__builtin_ppc_popcntb: {
+ Value *ArgValue = EmitScalarExpr(E->getArg(0));
+ llvm::Type *ArgType = ArgValue->getType();
+ Function *F = CGM.getIntrinsic(Intrinsic::ppc_popcntb, {ArgType, ArgType});
+ return Builder.CreateCall(F, Ops, "popcntb");
+ }
}
}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c b/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
index 6413f34fbc410..aaf3622a543a2 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
@@ -1,260 +1,471 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
-// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
-// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-32
+
+extern unsigned long a;
+extern const void *b;
+extern void *c;
-void test_popcntb() {
// CHECK-LABEL: @test_popcntb(
// CHECK-NEXT: entry:
-
- unsigned long a;
- unsigned long b = __popcntb(a);
-// CHECK: %1 = call i64 @llvm.ppc.popcntb(i64 %0)
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT: [[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
+// CHECK-NEXT: ret i64 [[POPCNTB]]
+//
+// CHECK-32-LABEL: @test_popcntb(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT: [[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
+// CHECK-32-NEXT: ret i32 [[POPCNTB]]
+//
+unsigned long test_popcntb() {
+ return __popcntb(a);
}
-void test_eieio() {
// CHECK-LABEL: @test_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.eieio()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_eieio(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.eieio()
+// CHECK-32-NEXT: ret void
+//
+void test_eieio() {
__eieio();
-// CHECK: call void @llvm.ppc.eieio()
}
-void test_iospace_eieio() {
// CHECK-LABEL: @test_iospace_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.iospace.eieio()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_iospace_eieio(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.iospace.eieio()
+// CHECK-32-NEXT: ret void
+//
+void test_iospace_eieio() {
__iospace_eieio();
-// CHECK: call void @llvm.ppc.iospace.eieio()
}
-void test_isync() {
// CHECK-LABEL: @test_isync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.isync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_isync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.isync()
+// CHECK-32-NEXT: ret void
+//
+void test_isync() {
__isync();
-// CHECK: call void @llvm.ppc.isync()
}
-void test_lwsync() {
// CHECK-LABEL: @test_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.lwsync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_lwsync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.lwsync()
+// CHECK-32-NEXT: ret void
+//
+void test_lwsync() {
__lwsync();
-// CHECK: call void @llvm.ppc.lwsync()
}
-void test_iospace_lwsync() {
// CHECK-LABEL: @test_iospace_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.iospace.lwsync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_iospace_lwsync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.iospace.lwsync()
+// CHECK-32-NEXT: ret void
+//
+void test_iospace_lwsync() {
__iospace_lwsync();
-// CHECK: call void @llvm.ppc.iospace.lwsync()
}
-void test_sync() {
// CHECK-LABEL: @test_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.sync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_sync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.sync()
+// CHECK-32-NEXT: ret void
+//
+void test_sync() {
__sync();
-// CHECK: call void @llvm.ppc.sync()
}
-void test_iospace_sync() {
// CHECK-LABEL: @test_iospace_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.iospace.sync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_iospace_sync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.iospace.sync()
+// CHECK-32-NEXT: ret void
+//
+void test_iospace_sync() {
__iospace_sync();
-// CHECK: call void @llvm.ppc.iospace.sync()
}
-void test_dcbfl() {
// CHECK-LABEL: @test_dcbfl(
-// CHECK-NEXT: entry:
-
- const void* a;
- __dcbfl(a);
-// CHECK: call void @llvm.ppc.dcbfl(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_dcbfl(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_dcbfl() {
+ __dcbfl(b);
}
-void test_dcbflp() {
// CHECK-LABEL: @test_dcbflp(
-// CHECK-NEXT: entry:
-
- const void* a;
- __dcbflp(a);
-// CHECK: call void @llvm.ppc.dcbflp(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_dcbflp(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_dcbflp() {
+ __dcbflp(b);
}
-void test_dcbst() {
// CHECK-LABEL: @test_dcbst(
-// CHECK-NEXT: entry:
-
- const void* a;
- __dcbst(a);
-// CHECK: call void @llvm.ppc.dcbst(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_dcbst(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_dcbst() {
+ __dcbst(b);
}
-void test_dcbt() {
// CHECK-LABEL: @test_dcbt(
-// CHECK-NEXT: entry:
-
- void* a;
- __dcbt(a);
-// CHECK: call void @llvm.ppc.dcbt(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_dcbt(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_dcbt() {
+ __dcbt(c);
}
-void test_dcbtst() {
// CHECK-LABEL: @test_dcbtst(
-// CHECK-NEXT: entry:
-
- void* a;
- __dcbtst(a);
-// CHECK: call void @llvm.ppc.dcbtst(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_dcbtst(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_dcbtst() {
+ __dcbtst(c);
}
-void test_dcbz() {
// CHECK-LABEL: @test_dcbz(
-// CHECK-NEXT: entry:
-
- void* a;
- __dcbz(a);
-// CHECK: call void @llvm.ppc.dcbz(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_dcbz(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_dcbz() {
+ __dcbz(c);
}
-void test_icbt() {
+// FIXME: __icbt is only valid for pwr8 and up.
// CHECK-LABEL: @test_icbt(
-// CHECK-NEXT: entry:
-
- void* a;
- __icbt(a);
-// CHECK: call void @llvm.ppc.icbt(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_icbt(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_icbt() {
+ __icbt(c);
}
-void test_builtin_ppc_popcntb() {
// CHECK-LABEL: @test_builtin_ppc_popcntb(
// CHECK-NEXT: entry:
-
- unsigned long a;
- unsigned long b = __builtin_ppc_popcntb(a);
-// CHECK: %1 = call i64 @llvm.ppc.popcntb(i64 %0)
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT: [[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
+// CHECK-NEXT: ret i64 [[POPCNTB]]
+//
+// CHECK-32-LABEL: @test_builtin_ppc_popcntb(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT: [[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
+// CHECK-32-NEXT: ret i32 [[POPCNTB]]
+//
+unsigned long test_builtin_ppc_popcntb() {
+ return __builtin_ppc_popcntb(a);
}
-void test_builtin_ppc_eieio() {
// CHECK-LABEL: @test_builtin_ppc_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.eieio()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_eieio(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.eieio()
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_eieio() {
__builtin_ppc_eieio();
-// CHECK: call void @llvm.ppc.eieio()
}
-void test_builtin_ppc_iospace_eieio() {
// CHECK-LABEL: @test_builtin_ppc_iospace_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.iospace.eieio()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_iospace_eieio(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.iospace.eieio()
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_iospace_eieio() {
__builtin_ppc_iospace_eieio();
-// CHECK: call void @llvm.ppc.iospace.eieio()
}
-void test_builtin_ppc_isync() {
// CHECK-LABEL: @test_builtin_ppc_isync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.isync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_isync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.isync()
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_isync() {
__builtin_ppc_isync();
-// CHECK: call void @llvm.ppc.isync()
}
-void test_builtin_ppc_lwsync() {
// CHECK-LABEL: @test_builtin_ppc_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.lwsync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_lwsync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.lwsync()
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_lwsync() {
__builtin_ppc_lwsync();
-// CHECK: call void @llvm.ppc.lwsync()
}
-void test_builtin_ppc_iospace_lwsync() {
// CHECK-LABEL: @test_builtin_ppc_iospace_lwsync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.iospace.lwsync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_iospace_lwsync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.iospace.lwsync()
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_iospace_lwsync() {
__builtin_ppc_iospace_lwsync();
-// CHECK: call void @llvm.ppc.iospace.lwsync()
}
-void test_builtin_ppc_sync() {
// CHECK-LABEL: @test_builtin_ppc_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.sync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_sync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.sync()
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_sync() {
__builtin_ppc_sync();
-// CHECK: call void @llvm.ppc.sync()
}
-void test_builtin_ppc_iospace_sync() {
// CHECK-LABEL: @test_builtin_ppc_iospace_sync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @llvm.ppc.iospace.sync()
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_iospace_sync(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @llvm.ppc.iospace.sync()
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_iospace_sync() {
__builtin_ppc_iospace_sync();
-// CHECK: call void @llvm.ppc.iospace.sync()
}
-void test_builtin_ppc_dcbfl() {
// CHECK-LABEL: @test_builtin_ppc_dcbfl(
-// CHECK-NEXT: entry:
-
- const void* a;
- __builtin_ppc_dcbfl(a);
-// CHECK: call void @llvm.ppc.dcbfl(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbfl(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbfl(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_dcbfl() {
+ __builtin_ppc_dcbfl(b);
}
-void test_builtin_ppc_dcbflp() {
// CHECK-LABEL: @test_builtin_ppc_dcbflp(
-// CHECK-NEXT: entry:
-
- const void* a;
- __builtin_ppc_dcbflp(a);
-// CHECK: call void @llvm.ppc.dcbflp(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbflp(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbflp(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_dcbflp() {
+ __builtin_ppc_dcbflp(b);
}
-void test_builtin_ppc_dcbst() {
// CHECK-LABEL: @test_builtin_ppc_dcbst(
-// CHECK-NEXT: entry:
-
- const void* a;
- __builtin_ppc_dcbst(a);
-// CHECK: call void @llvm.ppc.dcbst(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbst(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @b, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbst(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_dcbst() {
+ __builtin_ppc_dcbst(b);
}
-void test_builtin_ppc_dcbt() {
// CHECK-LABEL: @test_builtin_ppc_dcbt(
-// CHECK-NEXT: entry:
-
- void* a;
- __builtin_ppc_dcbt(a);
-// CHECK: call void @llvm.ppc.dcbt(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbt(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbt(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_dcbt() {
+ __builtin_ppc_dcbt(c);
}
-void test_builtin_ppc_dcbtst() {
// CHECK-LABEL: @test_builtin_ppc_dcbtst(
-// CHECK-NEXT: entry:
-
- void* a;
- __builtin_ppc_dcbtst(a);
-// CHECK: call void @llvm.ppc.dcbtst(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbtst(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbtst(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_dcbtst() {
+ __builtin_ppc_dcbtst(c);
}
-void test_builtin_ppc_dcbz() {
// CHECK-LABEL: @test_builtin_ppc_dcbz(
-// CHECK-NEXT: entry:
-
- void* a;
- __builtin_ppc_dcbz(a);
-// CHECK: call void @llvm.ppc.dcbz(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_dcbz(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.dcbz(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_dcbz() {
+ __builtin_ppc_dcbz(c);
}
-void test_builtin_ppc_icbt() {
+// FIXME: __icbt is only valid for pwr8 and up.
// CHECK-LABEL: @test_builtin_ppc_icbt(
-// CHECK-NEXT: entry:
-
- void* a;
- __builtin_ppc_icbt(a);
-// CHECK: call void @llvm.ppc.icbt(i8* %0)
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 8
+// CHECK-NEXT: call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-NEXT: ret void
+//
+// CHECK-32-LABEL: @test_builtin_ppc_icbt(
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i8*, i8** @c, align 4
+// CHECK-32-NEXT: call void @llvm.ppc.icbt(i8* [[TMP0]])
+// CHECK-32-NEXT: ret void
+//
+void test_builtin_ppc_icbt() {
+ __builtin_ppc_icbt(c);
}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index eb9126149019b..baa29dee3dcbb 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1534,12 +1534,12 @@ let TargetPrefix = "ppc" in {
[IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
def int_ppc_dcbz : GCCBuiltin<"__builtin_ppc_dcbz">,
Intrinsic<[], [llvm_ptr_ty], []>;
+// FIXME: __icbt is only valid for pwr8 and up.
def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
Intrinsic<[], [llvm_ptr_ty], []>;
// Population Count in each Byte.
- def int_ppc_popcntb : GCCBuiltin<"__builtin_ppc_popcntb">,
- Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
+ def int_ppc_popcntb : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
// sync instruction (i.e. sync 0, a.k.a hwsync)
def int_ppc_sync : GCCBuiltin<"__builtin_ppc_sync">,
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 76f52c7d88f45..8ef621c978661 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -138,6 +138,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
(instregex "SUBF(E|ME|ZE)?(8)?(O)?(_rec)?$"),
(instregex "NEG(8)?(O)?(_rec)?$"),
(instregex "POPCNTB$"),
+ (instregex "POPCNTB8$"),
(instregex "ADD(I|IS)?(8)?$"),
(instregex "LI(S)?(8)?$"),
(instregex "(X)?OR(I|IS)?(8)?(_rec)?$"),
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 931b7790b1d84..0e86a95eaba8d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -909,9 +909,10 @@ def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
"popcntw $rA, $rS", IIC_IntGeneral,
[(set i32:$rA, (ctpop i32:$rS))]>;
-def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS),
- "popcntb $rA, $rS", IIC_IntGeneral,
- [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>;
+let isCodeGenOnly = 1 in
+def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS),
+ "popcntb $rA, $rS", IIC_IntGeneral,
+ [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>;
defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"divd", "$rT, $rA, $rB", IIC_IntDivD,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 1658618800e90..ee3529ad70876 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2232,6 +2232,10 @@ def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
"td $to, $rA, $rB", IIC_IntTrapD, []>;
+def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS),
+ "popcntb $rA, $rS", IIC_IntGeneral,
+ [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>;
+
//===----------------------------------------------------------------------===//
// PPC32 Load Instructions.
//
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
index 2eefa59805f5c..2c9fd2034f887 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -1,33 +1,31 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
-; RUN: -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
-
-define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
-
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: --ppc-asm-full-reg-names -mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: msync
+; CHECK-NEXT: blr
entry:
call void @llvm.ppc.iospace.lwsync()
-; CHECK: msync
-
ret void
}
+declare void @llvm.ppc.iospace.lwsync()
-declare void @llvm.ppc.iospace.lwsync() #2
-
-define dso_local void @test_builtin_ppc_iospace_sync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_sync
-
+define dso_local void @test_builtin_ppc_iospace_sync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: msync
+; CHECK-NEXT: blr
entry:
call void @llvm.ppc.iospace.sync()
-; CHECK: msync
-
ret void
}
-
-declare void @llvm.ppc.iospace.sync() #2
-
+declare void @llvm.ppc.iospace.sync()
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
new file mode 100644
index 0000000000000..74cc1a0c7842c
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local i32 @test_builtin_ppc_popcntb_i32(i32 %a) local_unnamed_addr {
+; CHECK-LABEL: test_builtin_ppc_popcntb_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: popcntb 3, 3
+; CHECK-NEXT: blr
+entry:
+ %popcntb = tail call i32 @llvm.ppc.popcntb.i32.i32(i32 %a)
+ ret i32 %popcntb
+}
+declare i32 @llvm.ppc.popcntb.i32.i32(i32)
+
+define dso_local void @test_builtin_ppc_eieio() {
+; CHECK-LABEL: test_builtin_ppc_eieio:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+; CHECK-NEXT: blr
+entry:
+ call void @llvm.ppc.eieio()
+ ret void
+}
+declare void @llvm.ppc.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_eieio() {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+; CHECK-NEXT: blr
+entry:
+ call void @llvm.ppc.iospace.eieio()
+ ret void
+}
+declare void @llvm.ppc.iospace.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lwsync
+; CHECK-NEXT: blr
+entry:
+ call void @llvm.ppc.iospace.lwsync()
+ ret void
+}
+declare void @llvm.ppc.iospace.lwsync()
+
+define dso_local void @test_builtin_ppc_iospace_sync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sync
+; CHECK-NEXT: blr
+entry:
+ call void @llvm.ppc.iospace.sync()
+ ret void
+}
+declare void @llvm.ppc.iospace.sync()
+
+; FIXME: __icbt is only valid for pwr8 and up.
+define dso_local void @test_builtin_ppc_icbt() {
+; CHECK-LABEL: test_builtin_ppc_icbt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lwz 3, -8(1)
+; CHECK-NEXT: icbt 0, 0, 3
+; CHECK-NEXT: blr
+entry:
+ %a = alloca i8*, align 8
+ %0 = load i8*, i8** %a, align 8
+ call void @llvm.ppc.icbt(i8* %0)
+ ret void
+}
+declare void @llvm.ppc.icbt(i8*)
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
new file mode 100644
index 0000000000000..750039d66a3ce
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
@@ -0,0 +1,116 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+define dso_local i64 @test_builtin_ppc_popcntb_i64(i64 %a) local_unnamed_addr {
+; CHECK-LABEL: test_builtin_ppc_popcntb_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: popcntb r3, r3
+; CHECK-NEXT: blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_popcntb_i64:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT: popcntb 3, 3
+; CHECK-AIX-NEXT: blr
+entry:
+ %popcntb = tail call i64 @llvm.ppc.popcntb.i64.i64(i64 %a)
+ ret i64 %popcntb
+}
+declare i64 @llvm.ppc.popcntb.i64.i64(i64)
+
+define dso_local void @test_builtin_ppc_eieio() {
+; CHECK-LABEL: test_builtin_ppc_eieio:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
+; CHECK-NEXT: blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_eieio:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT: ori 2, 2, 0
+; CHECK-AIX-NEXT: ori 2, 2, 0
+; CHECK-AIX-NEXT: eieio
+; CHECK-AIX-NEXT: blr
+entry:
+ call void @llvm.ppc.eieio()
+ ret void
+}
+declare void @llvm.ppc.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_eieio() {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
+; CHECK-NEXT: blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_iospace_eieio:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT: ori 2, 2, 0
+; CHECK-AIX-NEXT: ori 2, 2, 0
+; CHECK-AIX-NEXT: eieio
+; CHECK-AIX-NEXT: blr
+entry:
+ call void @llvm.ppc.iospace.eieio()
+ ret void
+}
+declare void @llvm.ppc.iospace.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lwsync
+; CHECK-NEXT: blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_iospace_lwsync:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT: lwsync
+; CHECK-AIX-NEXT: blr
+entry:
+ call void @llvm.ppc.iospace.lwsync()
+ ret void
+}
+declare void @llvm.ppc.iospace.lwsync()
+
+define dso_local void @test_builtin_ppc_iospace_sync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sync
+; CHECK-NEXT: blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_iospace_sync:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT: sync
+; CHECK-AIX-NEXT: blr
+entry:
+ call void @llvm.ppc.iospace.sync()
+ ret void
+}
+declare void @llvm.ppc.iospace.sync()
+
+; FIXME: __icbt is only valid for pwr8 and up.
+define dso_local void @test_builtin_ppc_icbt() {
+; CHECK-LABEL: test_builtin_ppc_icbt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld r3, -8(r1)
+; CHECK-NEXT: icbt 0, 0, r3
+; CHECK-NEXT: blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_icbt:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT: ld 3, -8(1)
+; CHECK-AIX-NEXT: icbt 0, 0, 3
+; CHECK-AIX-NEXT: blr
+entry:
+ %a = alloca i8*, align 8
+ %0 = load i8*, i8** %a, align 8
+ call void @llvm.ppc.icbt(i8* %0)
+ ret void
+}
+declare void @llvm.ppc.icbt(i8*)
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
deleted file mode 100644
index 09530e8a62185..0000000000000
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-
-define dso_local void @test_builtin_ppc_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_eieio
-
-entry:
- call void @llvm.ppc.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
-
- ret void
-}
-
-declare void @llvm.ppc.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_eieio
-
-entry:
- call void @llvm.ppc.iospace.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
-
- ret void
-}
-
-declare void @llvm.ppc.iospace.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
-
-entry:
- call void @llvm.ppc.iospace.lwsync()
-; CHECK: lwsync
-
- ret void
-}
-
-declare void @llvm.ppc.iospace.lwsync() #2
-
-define dso_local void @test_builtin_ppc_iospace_sync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_sync
-
-entry:
- call void @llvm.ppc.iospace.sync()
-; CHECK: sync
-
- ret void
-}
-
-declare void @llvm.ppc.iospace.sync() #2
-
-define dso_local void @test_builtin_ppc_icbt() #0 {
-; CHECK-LABEL: test_builtin_ppc_icbt
-
-entry:
- %a = alloca i8*, align 8
- %0 = load i8*, i8** %a, align 8
- call void @llvm.ppc.icbt(i8* %0)
-; CHECK: icbt 0, 0, 3
-
- ret void
-}
-
-declare void @llvm.ppc.icbt(i8*) #2
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