[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.


================
Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15081
   }
+  case PPC::BI__builtin_ppc_cmpb: {
+    llvm::Type *Ty = Ops[0]->getType();
----------------
nemanjai wrote:
> I find it rather surprising that we are emitting this complex sequence for this builtin. Perhaps there is a good reason for doing so, but at the very least, this requires a thorough explanation in a comment.
> 
> One additional concern I have with this is that if some transformation proves that some portion of this is unused (perhaps using `DemandedBits` analysis), it may optimize out a portion of this, thereby making the sequence emit a whole bunch of xor's, or's, rotates, etc.
> 
> For example:
> ```
> ...
> unsigned long long A = __builtin_ppc_cmpb(B, C);
> return A & 0xFF00FF00FF00FF;
> ```
> It is entirely possible that the optimizer will get rid of some of the produced instructions and then the back end won't be able to emit a single `cmpb` but will have to emit a whole bunch of scalar instructions.
- The backend test case define i64 @test64(i64 %x, i64 %y) is in llvm/test/CodeGen/PowerPC/cmpb.ll
- Also Tried the test case and results look fine.
```
$ cat test_cmpb.c
long long test_cmpb(long long a, long long b) {
  //return __cmpb(a, b);
  unsigned long long A = __builtin_ppc_cmpb(a, b);
  return A & 0xFF00FF00FF00FF;
}
$ clang -cc1 -O3 -triple powerpc-unknown-aix test_cmpb.c -target-cpu pwr9 -S -o test_cmpb_32bit.s
...
.test_cmpb:
# %bb.0:                                # %entry
        cmpb 4, 6, 4
        lis 6, 255
        cmpb 3, 5, 3
        ori 6, 6, 255
        and 4, 4, 6
        and 3, 3, 6
        blr
$ clang -cc1 -O3 -triple powerpc64-unknown-aix test_cmpb.c -target-cpu pwr9 -S -o test_cmpb_64bit.s
.test_cmpb:
# %bb.0:                                # %entry
        cmpb 3, 4, 3
        lis 4, 255
        ori 4, 4, 255
        rldimi 4, 4, 32, 0
        and 3, 3, 4
        blr
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105194/new/

https://reviews.llvm.org/D105194