[PATCH] D94098: [Clang][AArch64] Inline assembly support for the ACLE type 'data512_t'.

[Eli Friedman via Phabricator via cfe-commits]

efriedma added a comment.

In D94098#2874976 <https://reviews.llvm.org/D94098#2874976>, @labrinea wrote:

> In D94098#2868751 <https://reviews.llvm.org/D94098#2868751>, @efriedma wrote:
>
>> 
>
> but in my honest opinion I don't see the benefit.

The problem is, there isn't really any point to supporting "register" operands in this state.  LLVM will never optimize an indirect register into a direct register, so we're guaranteed to generate an ld64b just before the inline asm block for inputs, and an st64b just after the inline asm block for outputs.  At that point, it's not really any better than something like `__asm__ volatile ("ld64b x0, [%0]; st64b x0,[%1]" : : "r" (input), "r" (output) : "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7" );`.

That is, unless we care about source compatibility with some other compiler that supports this, I guess.


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