[clang] 88326bb - [RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins
Ben Shi via cfe-commits
cfe-commits at lists.llvm.org
Thu Jul 8 22:19:05 PDT 2021
Author: jacquesguan
Date: 2021-07-09T13:18:42+08:00
New Revision: 88326bbce38c53f4782ba3b593b6720438a9569c
URL: https://github.com/llvm/llvm-project/commit/88326bbce38c53f4782ba3b593b6720438a9569c
DIFF: https://github.com/llvm/llvm-project/commit/88326bbce38c53f4782ba3b593b6720438a9569c.diff
LOG: [RISCV][clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins
Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only
with target feature Zvlsseg.
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D105626
Added:
Modified:
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
################################################################################
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
index 2c34788011afd..d279bd40961f2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
@@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
index 72a716702301e..6f0702cea3b02 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
@@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
index 37684ef3cdec8..1bbb5fa00564e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
@@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
index 856db27392ba8..ff6e740b37c05 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
@@ -2,12 +2,14 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 2381ab526792a..ea855314baca7 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -141,6 +141,7 @@ enum RISCVExtension : uint8_t {
D = 1 << 2,
Zfh = 1 << 3,
Zvamo = 1 << 4,
+ Zvlsseg = 1 << 5,
};
// TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -784,6 +785,8 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
}
if (RequiredExtension == "Zvamo")
RISCVExtensions |= RISCVExtension::Zvamo;
+ if (RequiredExtension == "Zvlsseg")
+ RISCVExtensions |= RISCVExtension::Zvlsseg;
// Init OutputType and InputTypes
OutputType = OutInTypes[0];
@@ -1237,6 +1240,8 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
OS << LS << "defined(__riscv_zfh)";
if (Extents & RISCVExtension::Zvamo)
OS << LS << "defined(__riscv_zvamo)";
+ if (Extents & RISCVExtension::Zvlsseg)
+ OS << LS << "defined(__riscv_zvlsseg)";
OS << "\n";
return true;
}
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