[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

[Victor Huang via Phabricator via cfe-commits]

NeHuang resigned from this revision.
NeHuang added inline comments.


================
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
----------------
Please use `pwr7` for BE test and `pwr8` for LE test.


================
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c:8
+// RUN: not %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 2>&1 | \
+// RUN:  FileCheck %s -check-prefixes=CHECK32-ERROR
----------------
pwr8 -> pwr7


================
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c:11
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN:  FileCheck %s --check-prefixes=CHECK64
----------------
pwr8 -> pwr7


================
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap.c:8
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN:  FileCheck %s
----------------
same as above


================
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-trap.c:11
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN:  FileCheck %s
----------------
same as above.


================
Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll:7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
----------------
same target cpu issue for the aix run lines in back end test cases.


================
Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:28
+}
+
+define dso_local void @test__tdweq(i64 %a, i64 %b) {
----------------
can you add another test case for `call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 3)` to verify the backend change below:
```
// tdne
def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 3),
          (TD 24, $A, $B)>;
```


================
Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:41
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    td 5, 3, 4
+; CHECK-NEXT:    blr
----------------
seems the InstAlias defined for `td` and `tw` not working as expected 



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  https://reviews.llvm.org/D103668/new/

https://reviews.llvm.org/D103668