[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

[Simon Pilgrim via Phabricator via cfe-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:64
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
 }
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You could avoid this change if you add a scheduler class to whatever instruction is complaining?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105269/new/

https://reviews.llvm.org/D105269