[PATCH] D105236: [PowerPC] Implament Atomic Load and Stores Builtins

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

The wording might be inaccurate. It's better to rephrase to 'Load and Reserve and Store Conditional'.



================
Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1724
+
+let Predicates = [HasP8Altivec] in {
+  def : Pat<(int_ppc_stdcx xoaddr:$dst, g8rc:$A),
----------------
IIRC, `l(w|d)arx`, `st(w|d)cx` are supported very early and don't need altivec support.


================
Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore-64-only.ll:7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK
+
----------------
Is `-mcpu=pwr9` necessary?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105236/new/

https://reviews.llvm.org/D105236