[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1148
+    if (HasPolicy) {
+      ProtoMaskSeq.push_back("z");
+    }
----------------
khchen wrote:
> maybe the policy argument should be a constant value ("Kz")?
Agreed.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:80
+
+  HasPolicyShift = HasVLOpShift + 1,
+  HasPolicyMask = 1 << HasPolicyShift,
----------------
This should be HasPolicyOpShift and HasPolicyOpMask to match SEWOp/VLOp naming.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:138
 
+static inline bool hasPolicy(uint64_t TSFlags) {
+  return TSFlags & HasPolicyMask;
----------------
hasPolicyOp


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:401
+    const MachineOperand &Op = MI.getOperand(NumOperands - 1);
+    TailAgnostic = Op.getImm();
+  }
----------------
Probably need to mask this to bit 0. `TailAgnostic = Op.getImm() & 1`. As written we'll set TailAgnostic if any bit in the immediate is non-zero.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:182
+
+  bit HasPolicy = false;
+  let TSFlags{16} = HasPolicy;
----------------
HasPolicyOp


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105092/new/

https://reviews.llvm.org/D105092