[PATCH] D104858: [OpenCL][ARM] Fix ICE when compiling a kernel

[Anastasia Stulova via Phabricator via cfe-commits]

Anastasia updated this revision to Diff 355166.
Anastasia retitled this revision from "[OpenCL][ARM] Fix ICE when compiling a source with the kernel" to "[OpenCL][ARM] Fix ICE when compiling a kernel".
Anastasia edited the summary of this revision.
Anastasia added reviewers: pekka, svenvh.
Anastasia added a subscriber: cfe-commits.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104858/new/

https://reviews.llvm.org/D104858

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl


Index: clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl
===================================================================
--- clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl
+++ clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl
@@ -1,9 +1,16 @@
 // RUN: %clang_cc1 %s -cl-std=CL1.2 -emit-llvm -triple x86_64-unknown-unknown -o - | FileCheck %s
 // RUN: %clang_cc1 %s -cl-std=CL1.2 -emit-llvm -triple amdgcn-unknown-unknown -o - | FileCheck -check-prefixes=AMDGCN %s
-// Test that the kernels always use the SPIR calling convention
-// to have unambiguous mapping of arguments to feasibly implement
+// RUN: %clang_cc1 %s -cl-std=CL1.2 -emit-llvm -triple arm -o - | FileCheck -check-prefixes=ARM %s
+// RUN: %clang_cc1 %s -cl-std=CL1.2 -emit-llvm -triple aarch64 -o - | FileCheck -check-prefixes=AARCH64 %s
+
+// Test that the kernels use the SPIR calling convention for targets that
+// support it.
+// This facilitates unambiguous mapping of arguments to feasibly implement
 // clSetKernelArg().
 
+// ARM-NOT: spir_kernel
+// AARCH64-NOT: spir_kernel
+
 typedef struct int_single {
     int a;
 } int_single;
@@ -21,7 +28,10 @@
     long elementE;
     float elementF;
     short elementG;
+// FIXME: double type should be enabled correctly for Arm CPU.
+#if !defined(__ARM_ARCH)
     double elementH;
+#endif
 } test_struct;
 
 kernel void test_single(int_single input, global int* output) {
@@ -53,7 +63,9 @@
  output[4] = (int)input.elementE;
  output[5] = (int)input.elementF;
  output[6] = (int)input.elementG;
+#if !defined(__ARM_ARCH)
  output[7] = (int)input.elementH;
+#endif
 };
 
 void test_function(int_pair input, global int* output) {
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -5523,6 +5523,12 @@
     Fn->addFnAttr("branch-target-enforcement",
                   BPI.BranchTargetEnforcement ? "true" : "false");
   }
+
+  unsigned getOpenCLKernelCallingConv() const override {
+    // OpenCL kernels use calling convention from the regular functions
+    // as there is no special support for threads.
+    return llvm::CallingConv::C;
+  }
 };
 
 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
@@ -6328,6 +6334,12 @@
     B.addStackAlignmentAttr(8);
     Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
   }
+
+  unsigned getOpenCLKernelCallingConv() const override {
+    // OpenCL kernels use calling convention from the regular functions
+    // as there is no special support for threads.
+    return llvm::CallingConv::C;
+  }
 };
 
 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D104858.355166.patch
Type: text/x-patch
Size: 2738 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20210629/78235172/attachment-0001.bin>