[clang] 7a11235 - [X86] Correct the conversion of VALIGND/Q intrinsics to shufflevector.

[Craig Topper via cfe-commits]

Author: Craig Topper
Date: 2021-06-26T19:06:00-07:00
New Revision: 7a112356e4a19c0e63f533548fa95a03a5537fb9

URL: https://github.com/llvm/llvm-project/commit/7a112356e4a19c0e63f533548fa95a03a5537fb9
DIFF: https://github.com/llvm/llvm-project/commit/7a112356e4a19c0e63f533548fa95a03a5537fb9.diff

LOG: [X86] Correct the conversion of VALIGND/Q intrinsics to shufflevector.

We need to mask the immediate to the width of a single vector
rather than 2 vectors. If we use the width of 2 vectors then
any shift larger than the length of 1 vector is going to overflow
the shuffle indices.

Fixes PR50895.

Added: 
    

Modified: 
    clang/lib/CodeGen/CGBuiltin.cpp
    clang/test/CodeGen/X86/avx512vl-builtins.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e8ad4e009bfb2..97f2db9bec2c8 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -13376,8 +13376,8 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
         cast<llvm::FixedVectorType>(Ops[0]->getType())->getNumElements();
     unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff;
 
-    // Mask the shift amount to width of two vectors.
-    ShiftVal &= (2 * NumElts) - 1;
+    // Mask the shift amount to width of a vector.
+    ShiftVal &= NumElts - 1;
 
     int Indices[16];
     for (unsigned i = 0; i != NumElts; ++i)

diff  --git a/clang/test/CodeGen/X86/avx512vl-builtins.c b/clang/test/CodeGen/X86/avx512vl-builtins.c
index ef27542876a43..4a7226489f573 100644
--- a/clang/test/CodeGen/X86/avx512vl-builtins.c
+++ b/clang/test/CodeGen/X86/avx512vl-builtins.c
@@ -9426,7 +9426,7 @@ __m128i test_mm_mask_alignr_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128
   // CHECK-LABEL: @test_mm_mask_alignr_epi32
   // CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
   // CHECK: select <4 x i1> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}
-  return _mm_mask_alignr_epi32(__W, __U, __A, __B, 1);
+  return _mm_mask_alignr_epi32(__W, __U, __A, __B, 5);
 }
 
 __m128i test_mm_maskz_alignr_epi32(__mmask8 __U, __m128i __A, __m128i __B) {
@@ -9446,7 +9446,7 @@ __m256i test_mm256_mask_alignr_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m
   // CHECK-LABEL: @test_mm256_mask_alignr_epi32
   // CHECK: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
   // CHECK: select <8 x i1> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> %{{.*}}
-  return _mm256_mask_alignr_epi32(__W, __U, __A, __B, 1);
+  return _mm256_mask_alignr_epi32(__W, __U, __A, __B, 9);
 }
 
 __m256i test_mm256_maskz_alignr_epi32(__mmask8 __U, __m256i __A, __m256i __B) {
@@ -9466,7 +9466,7 @@ __m128i test_mm_mask_alignr_epi64(__m128i __W, __mmask8 __U, __m128i __A, __m128
   // CHECK-LABEL: @test_mm_mask_alignr_epi64
   // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i32> <i32 1, i32 2>
   // CHECK: select <2 x i1> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}
-  return _mm_mask_alignr_epi64(__W, __U, __A, __B, 1);
+  return _mm_mask_alignr_epi64(__W, __U, __A, __B, 3);
 }
 
 __m128i test_mm_maskz_alignr_epi64(__mmask8 __U, __m128i __A, __m128i __B) {
@@ -9486,7 +9486,7 @@ __m256i test_mm256_mask_alignr_epi64(__m256i __W, __mmask8 __U, __m256i __A, __m
   // CHECK-LABEL: @test_mm256_mask_alignr_epi64
   // CHECK: shufflevector <4 x i64> %{{.*}}, <4 x i64> %{{.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
   // CHECK: select <4 x i1> %{{.*}}, <4 x i64> %{{.*}}, <4 x i64> %{{.*}}
-  return _mm256_mask_alignr_epi64(__W, __U, __A, __B, 1);
+  return _mm256_mask_alignr_epi64(__W, __U, __A, __B, 5);
 }
 
 __m256i test_mm256_maskz_alignr_epi64(__mmask8 __U, __m256i __A, __m256i __B) {