[PATCH] D104854: Introduce intrinsic llvm.isnan
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Fri Jun 25 10:28:48 PDT 2021
craig.topper added inline comments.
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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:662
+ EVT NewResultVT = TLI.getTypeToTransformTo(*DAG.getContext(), ResultVT);
+ return DAG.getNode(N->getOpcode(), DL, NewResultVT, N->getOperand(0));
+}
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Don't you net to preserve the NoFPExcept flag? Same with all the other type legalization functions
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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:600
+
+ SDValue Res = DAG.getNode(ISD::ISNAN, DL, ResultVT, Arg);
+ // Vectors may have a different boolean contents to scalars. Promote the
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If this is ResultVT then the Extend created next is always a NOP. Should this be MVT::i1?
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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:4727
+
+ if (TLI.isTypeLegal(WideResultVT)) {
+ SDValue WideNode = DAG.getNode(ISD::ISNAN, DL, WideResultVT, WideArg);
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I wonder if we should be using getSetCCResultType here like WidenVecOp_SETCC?
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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:6371
+ DAG.getNode(ISD::ISNAN, sdl, DestVT, getValue(I.getArgOperand(0)));
+ V->setFlags(Flags);
+ // If ISD::ISNAN should be expanded, do it right now, because the expansion
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Why not pass flags to getNode?
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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:6375
+ // types prior to selection.
+ if (!TLI.isOperationLegalOrCustom(ISD::ISNAN, ArgVT)) {
+ SDValue Result = TLI.expandISNAN(V.getNode(), DAG);
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This breaks if we add constant folding for ISD::ISNAN to getNode.
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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6981
+ // V = sign bit (Sub) <=> V = (Sub < 0)
+ SDValue SignBitV = DAG.getNode(ISD::SRL, DL, IntVT, Sub,
+ DAG.getConstant(BitSize - 1, DL, IntVT));
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Why can't we just check < 0 here? Why do we need to shift?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D104854/new/
https://reviews.llvm.org/D104854
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