[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: nemanjai, jsji, xingxue, hubert.reinterpretcast, cebowleratibm, PowerPC.
Herald added subscribers: jfb, kbarton.
Herald added a reviewer: jfb.
lkail requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

If target cpu is pwr8+, we can generate inlined quadword lock free atomic operations, thus no need to generate libcalls into libatomic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103501

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/ppc64-quadword-atomics.c


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, &new, &old, __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===================================================================
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+    if (getTriple().isOSAIX() && getTriple().isArch64Bit() &&
+        hasFeature("quadword-atomics"))
+      MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::CharPtrBuiltinVaList;
   }
Index: clang/lib/Basic/Targets/PPC.cpp
===================================================================
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,8 @@
       HasROPProtect = true;
     } else if (Feature == "+privileged") {
       HasPrivileged = true;
+    } else if (Feature == "+quadword-atomics") {
+      HasQuadwordAtomics = true;
     }
     // TODO: Finish this list and add an assert that we've handled them
     // all.
@@ -331,6 +333,11 @@
                         .Case("pwr9", true)
                         .Case("pwr8", true)
                         .Default(false);
+  Features["quadword-atomics"] = llvm::StringSwitch<bool>(CPU)
+                                     .Case("pwr10", true)
+                                     .Case("pwr9", true)
+                                     .Case("pwr8", true)
+                                     .Default(false);
 
   // ROP Protect is off by default.
   Features["rop-protect"] = false;
@@ -428,6 +435,7 @@
       .Case("mma", HasMMA)
       .Case("rop-protect", HasROPProtect)
       .Case("privileged", HasPrivileged)
+      .Case("quadword-atomics", HasQuadwordAtomics)
       .Default(false);
 }
 


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