[PATCH] D100782: [PowerPC] Improve f32 to i32 bitcast code gen

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.

Please add the missing BE handling.



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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2800
+                               (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))),
+          (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 0), (XSCVDPSP f64:$A), sub_64), 0))>;
 def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
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Although it is accurate that this specific instruction clears the other bits, all the other uses of `SUBREG_TO_REG` in the back end use `(i64 1)` and I don't think it is particularly useful to part with that here.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:4276
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),
+          (v4f32 (XXINSERTW v4f32:$A,
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These also need to be added for big endian subtargets.


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Comment at: llvm/test/CodeGen/PowerPC/vec_insert_elt.ll:741
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xsrsp f0, f1
+; CHECK-BE-NEXT:    xscvdpspn vs0, f0
----------------
Notice that this still generates the undesired code due to missing the new patterns for big endian subtargets.


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  https://reviews.llvm.org/D100782/new/

https://reviews.llvm.org/D100782