[PATCH] D101191: [InstCombine] Fully disable select to and/or i1 folding

[Juneyoung Lee via Phabricator via cfe-commits]

aqjune updated this revision to Diff 342624.
aqjune added a comment.

Rebase onto D101807 <https://reviews.llvm.org/D101807>


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101191/new/

https://reviews.llvm.org/D101191

Files:
  clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
  llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
  llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
  llvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
  llvm/test/Transforms/InstCombine/and-fcmp.ll
  llvm/test/Transforms/InstCombine/and-or-icmp-min-max.ll
  llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll
  llvm/test/Transforms/InstCombine/and-or-icmps.ll
  llvm/test/Transforms/InstCombine/and.ll
  llvm/test/Transforms/InstCombine/and2.ll
  llvm/test/Transforms/InstCombine/assume.ll
  llvm/test/Transforms/InstCombine/bit-checks.ll
  llvm/test/Transforms/InstCombine/demorgan.ll
  llvm/test/Transforms/InstCombine/div-by-0-guard-before-smul_ov-not.ll
  llvm/test/Transforms/InstCombine/div-by-0-guard-before-smul_ov.ll
  llvm/test/Transforms/InstCombine/div-by-0-guard-before-umul_ov-not.ll
  llvm/test/Transforms/InstCombine/div-by-0-guard-before-umul_ov.ll
  llvm/test/Transforms/InstCombine/dont-distribute-phi.ll
  llvm/test/Transforms/InstCombine/icmp.ll
  llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
  llvm/test/Transforms/InstCombine/logical-select.ll
  llvm/test/Transforms/InstCombine/onehot_merge.ll
  llvm/test/Transforms/InstCombine/or-fcmp.ll
  llvm/test/Transforms/InstCombine/or.ll
  llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll
  llvm/test/Transforms/InstCombine/range-check.ll
  llvm/test/Transforms/InstCombine/select-and-or.ll
  llvm/test/Transforms/InstCombine/select-bitext.ll
  llvm/test/Transforms/InstCombine/select-cmp-br.ll
  llvm/test/Transforms/InstCombine/select-safe-bool-transforms.ll
  llvm/test/Transforms/InstCombine/select-safe-impliedcond-transforms.ll
  llvm/test/Transforms/InstCombine/select-safe-transforms.ll
  llvm/test/Transforms/InstCombine/select.ll
  llvm/test/Transforms/InstCombine/sign-test-and-or.ll
  llvm/test/Transforms/InstCombine/signed-truncation-check.ll
  llvm/test/Transforms/InstCombine/umul-sign-check.ll
  llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll
  llvm/test/Transforms/InstCombine/widenable-conditions.ll
  llvm/test/Transforms/InstCombine/zext-or-icmp.ll
  llvm/test/Transforms/LoopSimplify/merge-exits.ll
  llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
  llvm/test/Transforms/PGOProfile/chr.ll
  llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
  llvm/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll

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