[clang] bfd60b3 - [PowerPC] Add floating point overloads for vec_sldw

[Nemanja Ivanovic via cfe-commits]

Author: Nemanja Ivanovic
Date: 2021-04-30T20:29:03-05:00
New Revision: bfd60b36f825c299971bb0c2bf973031e2e0fc09

URL: https://github.com/llvm/llvm-project/commit/bfd60b36f825c299971bb0c2bf973031e2e0fc09
DIFF: https://github.com/llvm/llvm-project/commit/bfd60b36f825c299971bb0c2bf973031e2e0fc09.diff

LOG: [PowerPC] Add floating point overloads for vec_sldw

These are added for compatibility with XLC.

Added: 
    

Modified: 
    clang/lib/Headers/altivec.h
    clang/test/CodeGen/builtins-ppc-altivec.c
    clang/test/CodeGen/builtins-ppc-vsx.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 04d4a5b16c5c..cb4f35caf4d4 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -9091,6 +9091,11 @@ static __inline__ vector unsigned int __ATTRS_o_ai vec_sldw(
   return vec_sld(__a, __b, ((__c << 2) & 0x0F));
 }
 
+static __inline__ vector float __ATTRS_o_ai vec_sldw(
+    vector float __a, vector float __b, unsigned const int __c) {
+  return vec_sld(__a, __b, ((__c << 2) & 0x0F));
+}
+
 #ifdef __VSX__
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_sldw(vector signed long long __a, vector signed long long __b,
@@ -9103,6 +9108,11 @@ vec_sldw(vector unsigned long long __a, vector unsigned long long __b,
          unsigned const int __c) {
   return vec_sld(__a, __b, ((__c << 2) & 0x0F));
 }
+
+static __inline__ vector double __ATTRS_o_ai vec_sldw(
+    vector double __a, vector double __b, unsigned const int __c) {
+  return vec_sld(__a, __b, ((__c << 2) & 0x0F));
+}
 #endif
 
 #ifdef __POWER9_VECTOR__

diff  --git a/clang/test/CodeGen/builtins-ppc-altivec.c b/clang/test/CodeGen/builtins-ppc-altivec.c
index e0efebd8e3c7..e7593ca9021c 100644
--- a/clang/test/CodeGen/builtins-ppc-altivec.c
+++ b/clang/test/CodeGen/builtins-ppc-altivec.c
@@ -3759,6 +3759,18 @@ void test6() {
   // CHECK-LE: sub nsw i32 31
   // CHECK-LE: @llvm.ppc.altivec.vperm
 
+  res_vf = vec_sldw(vf, vf, 0);
+  // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
+  // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
+  // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
+  // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
+  // CHECK: @llvm.ppc.altivec.vperm
+  // CHECK-LE: sub nsw i32 16
+  // CHECK-LE: sub nsw i32 17
+  // CHECK-LE: sub nsw i32 18
+  // CHECK-LE: sub nsw i32 31
+  // CHECK-LE: @llvm.ppc.altivec.vperm
+
   res_vsc = vec_vsldoi(vsc, vsc, 0);
 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2

diff  --git a/clang/test/CodeGen/builtins-ppc-vsx.c b/clang/test/CodeGen/builtins-ppc-vsx.c
index 3614fe709814..ecae9a620e42 100644
--- a/clang/test/CodeGen/builtins-ppc-vsx.c
+++ b/clang/test/CodeGen/builtins-ppc-vsx.c
@@ -1888,6 +1888,18 @@ void test1() {
 // CHECK-LE: sub nsw i32 17
 // CHECK-LE: sub nsw i32 18
 // CHECK-LE: sub nsw i32 31
+// CHECK-LE: @llvm.ppc.altivec.vperm
+
+  res_vd = vec_sldw(vd, vd, 0);
+// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
+// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
+// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
+// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
+// CHECK: @llvm.ppc.altivec.vperm
+// CHECK-LE: sub nsw i32 16
+// CHECK-LE: sub nsw i32 17
+// CHECK-LE: sub nsw i32 18
+// CHECK-LE: sub nsw i32 31
 // CHECK-LE: @llvm.ppc.altivec.vperm
 
   res_vsll = vec_sll(vsll, vuc);