[PATCH] D100819: [RISCV] Implement the vneg.v builtin.
Zakk Chen via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Apr 21 03:03:35 PDT 2021
khchen added inline comments.
================
Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c:3
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN: -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
----------------
nit: The integer intrinsic functions do not need the -target-feature +f, +d and +experimental-zfh.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D100819/new/
https://reviews.llvm.org/D100819
More information about the cfe-commits
mailing list