[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:33
 def riscv_shfl   : SDNode<"RISCVISD::SHFL",   SDTIntBinOp>;
+def riscv_shflw   : SDNode<"RISCVISD::SHFLW",   SDT_RISCVIntBinOpW>;
+def riscv_unshfl   : SDNode<"RISCVISD::UNSHFL",   SDTIntBinOp>;
----------------
Line the colons up


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:749
 def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>;
+def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
 } // Predicates = [HasStdExtZbp]
----------------
Put this between riscv_shfl and riscv_grev so that shfl and unshfl are together


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:946
+let Predicates = [HasStdExtZbp] in {
+def : PatGprGpr<riscv_grev, GREV>;
+def : PatGprGpr<riscv_gorc, GORC>;
----------------
Put these in the same block that has PatGprImm<riscv_grev


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Comment at: llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll:92
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 29
+; RV32IB-NEXT:    shfl a0, a0, a1
----------------
This immediate is too large to make shfli. It needs to b 4 bits for i32.


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Comment at: llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll:126
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    addi a1, zero, 29
+; RV32IB-NEXT:    unshfl a0, a0, a1
----------------
Same here


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Comment at: llvm/test/MC/RISCV/rv32b-aliases-valid.s:256
+# CHECK-S-OBJ: shfli t0, t1, 29
+shfl x5, x6, 29
+
----------------
This test fails check-llvm because 29 isn't a shfl_uimm on RV32


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D100830/new/

https://reviews.llvm.org/D100830