[PATCH] D100782: [PowerPC] Improve f32 to i32 bitcast code gen

[Albion Fung via Phabricator via cfe-commits]

Conanap created this revision.
Conanap added reviewers: saghir, nemanjai, PowerPC.
Conanap added projects: PowerPC, clang, LLVM.
Herald added a subscriber: kbarton.
Conanap requested review of this revision.

The code gen for f32 to i32 bitcast is not currently the most efficient. For example:

  int foo(float f) {
    return *(int*)&f;
  }

Generates:

  xscvdpspn vs0, f1
  xxsldwi vs0, vs0, vs0, 3
  mffprwz	r3, f0

However, `xxsldwi` is actually not needed as `xscvdpspn` already splats the value.

This patch removes that instruction for this specific code gen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100782

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
  llvm/test/CodeGen/PowerPC/vec_insert_elt.ll


Index: llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
+++ llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
@@ -200,21 +200,19 @@
 ; CHECK-LABEL: testFloat1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpspn vs0, f1
-; CHECK-NEXT:    extsw r3, r6
-; CHECK-NEXT:    slwi r3, r3, 2
-; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; CHECK-NEXT:    mffprwz r4, f0
-; CHECK-NEXT:    vinswrx v2, r3, r4
+; CHECK-NEXT:    extsw r4, r6
+; CHECK-NEXT:    slwi r4, r4, 2
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    vinswrx v2, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testFloat1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpspn vs0, f1
-; CHECK-BE-NEXT:    extsw r3, r6
-; CHECK-BE-NEXT:    slwi r3, r3, 2
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    vinswlx v2, r3, r4
+; CHECK-BE-NEXT:    extsw r4, r6
+; CHECK-BE-NEXT:    slwi r4, r4, 2
+; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    vinswlx v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloat1:
Index: llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
+++ llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
@@ -10,8 +10,8 @@
 ; CHECK-P7: stfs 1,
 ; CHECK-P7: lwa 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
 }
 
 define i64 @f64toi64(double %a) {
@@ -50,8 +50,8 @@
 ; CHECK-P7: stfs 1,
 ; CHECK-P7: lwz 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
 }
 
 define i64 @f64toi64u(double %a) {
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1814,8 +1814,7 @@
 
 // Output dag used to bitcast f32 to i32 and f64 to i64
 def Bitcast {
-  dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI (XSCVDPSPN $A),
-                      (XSCVDPSPN $A), 3), sub_64)));
+  dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64)));
   dag DblToLong = (i64 (MFVSRD $A));
 }
 


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