[PATCH] D97264: [RISCV] Define types for Zvlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added a comment.

In D97264#2663082 <https://reviews.llvm.org/D97264#2663082>, @rogfer01 wrote:

> I was under the impression we didn't want to use class-member access syntax for vector tuples (see https://github.com/riscv/rvv-intrinsic-doc/issues/17#issuecomment-628998077 ) so we don't need a record type, do we?
>
> Perhaps it is possible to model them like opaque entities similar to what we do with RVV vectors where they are expanded in `CodegenTypes.cpp`?
>
> Access to fields would have to be through intrinsics, though I think this didn't scale very well, did it?

Do you mean treat the Zvlsseg types as kind of builtin types? I want to avoid to add too much builtin types in Clang. That is why I use implicit defined RecordType for Zvlsseg types.


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